h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 190

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

7.3.1
DMSAR is a 32-bit readable/writable register that specifies the transfer source address. An address
update function is provided that updates the register contents to the next transfer source address
each time transfer processing is performed. In single address mode, the DMSAR value is ignored
when a device with DACK is specified as the transfer source.
The upper 8 bits of DMSAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
The DMSAR value is undefined at a reset or in hardware standby mode.
Do not write to DMSAR for a channel on which DMA transfer is in progress.
DMSAR can be read at all times by the CPU. When reading DMSAR for a channel on which
DMA transfer processing is in progress, a longword-size read must be executed.
7.3.2
DMDAR is a 32-bit readable/writable register that specifies the transfer destination address. An
address update function is provided that updates the register contents to the next transfer
destination address each time transfer processing is performed. In single address mode, the
DMDAR value is ignored when a device with DACK is specified as the transfer destination.
The upper 8 bits of DMDAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
The DMDAR value is undefined at a reset or in hardware standby mode.
Do not write to DMDAR for a channel on which DMA transfer is in progress.
DMDAR can be read at all times by the CPU. When reading DMDAR for a channel on which
DMA transfer processing is in progress, a longword-size read must be executed.
7.3.3
DMTCR specifies the number of transfers. The function differs according to the transfer mode
(normal/block).
The DMTCR value is undefined at a reset or in hardware standby mode.
Do not write to DMTCR for a channel on which DMA transfer is in progress.
Rev. 2.00, 03/04, page 158 of 534
DMA Source Address Register (DMSAR)
DMA Destination Address Register (DMDAR)
DMA Transfer Count Register (DMTCR)