h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 380
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 380 of 570
- Download datasheet (5Mb)
5. Status Stage (Control-Out)
Rev. 2.00, 03/04, page 348 of 534
The control-out status stage starts with an IN token from the host. When an IN-token is
received at the start of the status stage, there is not yet any data in the EP0i FIFO, and so an
EP0i transfer request interrupt is generated. The firmware recognizes from this interrupt that
the status stage has started. Next, in order to transmit 0-length packet to the host, 0 is written in
the packet enable register 0i but no data is written to the EP0i FIFO. As a result, the next IN
token causes 0-length packet to be transmitted to the host, and control transfer ends.
After the firmware has finished all processing relating to the data stage, 0 should be written in
the packet enable register 0i.
Set EP0i transmit complete flag
End of control transfer
Is SETUP TS in IFR0
Transmit data to host
(EP0i TS in IFR0 = 1)
Receive IN token
in EP0i FIFO?
USB function
cleared to 0?
Valid data
Figure 12.9 Status Stage Operation (Control-Out)
Yes
Yes
ACK
No
No
NAK
NAK
Interrupt generated
generated
Interrupt
Write 0 to packet enable register 0i
prohibited (EP0i TR in IER0 = 0)
EP0i transfer request interrupt
End of control transfer
(EP0i TR in IFR0 = 0)
(EP0i TS in IFR0 = 0)
Clear interrupt flag
Clear interrupt flag
Firmware
(PKTE0i)
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