h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 87

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h8s-2172

Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
4.1
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority.
Table 4.1
Priority
High
Low
Exception Handling Types and Priority
Exception Type
Interrupt
Trap instruction
Reset
Exception Types and Priority
Section 4 Exception Handling
Start of Exception Handling
Starts immediately after a low-to-high transition of the RES
pin, or when the watchdog timer overflows.
Starts when execution of the current instruction or
exception handling ends, if an interrupt request has been
issued. Interrupt detection is not performed on completion
of ANDC, ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
Started by execution of a trap (TRAPA) instruction. Trap
instruction exception handling requests are accepted at all
times in program execution state.
Rev. 2.00, 03/04, page 55 of 534

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