AD5412_09 AD [Analog Devices], AD5412_09 Datasheet - Page 8

• Manufacturer Part Number: AD5412_09
• Description: Single Channel, 12-/16-Bit, Serial Input, Current Source and Voltage Output DACs
• Manufacturer: AD [Analog Devices]

AD5412/AD5422
TIMING CHARACTERISTICS
AV
V
Table 4.
Parameter
WRITE MODE
READBACK MODE
DAISY-CHAIN MODE
1
2
3
4
Guaranteed by characterization; not production tested.
All input signals are specified with t
See Figure 2, Figure 3, and Figure 4.
C
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
OUT
1
2
3
4
5
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
L SDO
DD
: R
= capacitive load on SDO output.
= 10.8 V to 26.4 V, AV
LOAD
1, 2, 3
= 1 kΩ, C
L
= 200 pF, I
Limit at T
33
13
13
13
40
5
5
5
40
20
5
90
40
40
13
40
5
5
40
35
35
90
40
40
13
40
5
5
40
35
SS
= −26.4 V to −3 V/0 V, AV
R
= t
MIN
F
OUT
= 5 ns (10% to 90% of DV
, T
: R
MAX
LOAD
= 300 Ω; all specifications T
Unit
ns min
ns min
ns min
ns min
ns min
μs min
ns min
ns min
ns min
ns min
μs max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
CC
) and timed from a voltage level of 1.2 V.
DD
+ |AV
Rev. A | Page 8 of 40
Description
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
LATCH high time (after a write to the control register)
Data setup time
Data hold time
LATCH low time
CLEAR pulse width
CLEAR activation time
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (C
LATCH rising edge to SDO tristate (C
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (C
SS
| < 52.8V, GND = 0 V, REFIN = +5 V external; DV
MIN
to T
MAX
, unless otherwise noted.
L SDO
L SDO
4
4
= 15 pF)
= 15 pF)
L SDO
4
= 15 pF)
CC
= 2.7 V to 5.5 V.