AD5522JSVD AD [Analog Devices], AD5522JSVD Datasheet - Page 19

• Manufacturer Part Number: AD5522JSVD
• Description: Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
FUNCTIONAL DESCRIPTION
The AD5522 is a highly integrated quad per pin parametric
measurement unit (PPMU) for use in semiconductor automatic
test equipment. It contains programmable modes to force a pin
voltage and measure the corresponding current (FVMI), force
current measure voltage (FIMV), force current measure current
(FIMI), force voltage measure voltage (FVMV) and force
nothing measure voltage (FNMV) or measure current (FNMI).
The PPMU can force or measure a voltage range of 22.5 V. It
can force or measure currents ranging up to 64mA per channel
using the internal amplifier, while the addition of an external
amplifier enables higher current ranges. On Chip are all the
DAC levels required for each PMU channel.
FORCE AMPLIFIER
The force amplifier drives the analog output FOH, which drives
a programmed current or voltage to the DUT (device under
test). Headroom and footroom requirements for this amplifier
is 3V on either end. An additional ±1V is dropped across the
sense resistor when maximum current is flowing through it.
This amplifier is designed to drive DUT capacitances up to
10nF, with a compensation value of 100pF. Larger DUT
capacitive load will require larger compensation capacitances.
Local feedback ensures the amplifiers are stable when disabled.
A disabled channel reduces power consumption by
2.5mA/channel.
COMPARATORS
Per channel, the DUT measured value is monitored by two
comparators configured as window comparators. Internal DAC
levels set the CPL and CPH (low and high) threshold values.
There are no restrictions on the voltage settings of the
comparator high and lows. CPL going higher than CPH is not a
useful operation; however, it will not cause any problems to the
device. CPOL and CPOH are continuous time comparator
outputs.
Table 7. Comparator Output Function
TEST CONDITION
V
V
V
V
When using SPI interface, full comparator functionality is
available. When using the LVDS interface, the comparator
function is limited to one output per comparator, due to the
large pin count requirement of the LVDS interface. In this case,
CPH > V
DUT
DUT
DUT
DUT
or I
or I
or I
or I
DUT
DUT
DUT
DUT
DUT
> CPH
< CPH
< CPL
> CPL
or I
DUT
> CPL
CPOL
1
0
1
CPOH
0
1
1
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comparator output available CPO (0-3) provides information
on whether the measured voltage or current is inside or outside
the set CPH and CPL window. Information of whether the
measurement was high or low is available via the serial
interfaces (Comparator Status Register).
Table 8. Comparator Output Function using LVDS interface
TEST CONDITION
CPL < V
CPL > V
CLAMPS
Current and voltage clamps are included on chip per PMU
channel. They protect the DUT in the event of an open or a
short. Internal DAC levels set the CLL and CLH (low and high)
levels and the clamps work to limit the force amplifier in the
event of a voltage or current at the DUT exceeding the set levels.
The clamps also function to protect the DUT when a transient
voltage or current spike occurs when changing to a different
operating mode or when programming the device to a different
current range.
The voltage clamps are active while forcing current and the
current clamps are active while forcing voltage. By default, the
current clamps are off. Simply set them up via the status register
through the serial interface. The voltage clamps are always
active in FI mode.
If a clamp level has been hit, this will be flagged via the CGALM
open drain output and the resulting alarm information may be
read back via the SPI or LVDS interface. CLL should never be
greater than CLH.
DUT
DUT
And I
or I
DUT
DUT
> CPH
< CPH
CPO Output
1
0
AD5522