AD5522JSVD AD [Analog Devices], AD5522JSVD Datasheet - Page 28

• Manufacturer Part Number: AD5522JSVD
• Description: Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
• Manufacturer: AD [Analog Devices]

AD5522
SERIAL INTERFACE
The AD5522 contains two high-speed serial interfaces, an SPI
compatible, interface operating at clock frequencies up to
50MHz, and an EIA-644-compliant, LVDS interface. To
minimize both the power consumption of the device and on-
chip digital noise, the interface powers up fully only when the
device is being written to, that is, on the falling edge of SYNC .
SPI INTERFACE
The serial interface operates over a 2.3V to 5.25V DV
range. The serial interface is controlled by four pin, as follows:
SYNC Frame synchronization input.
SDI Serial data input pin.
SCLK Clocks data in and out of the device.
SDO Serial data output pin for data readback purposes.
There is also an SPI /LVDS select pin, which must be held low
for SPI interface and high for LVDS interface.
LVDS INTERFACE
The LVDS interface uses the same input pins as the SPI
interface with the same designations. In addition, three other
pins are provided for the complementary signals needed for
differential operation, thus:
SYNC/ SYNC Differential frame synchronization signal.
SDI/ SDI Differential serial data input.
SCLK/ SCLK Differential clock input.
SDO/ SDO Serial data output pin for data readback
SERIAL INTERFACE WRITE MODE
The AD5522 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which is
all registers except the DAC registers.
The serial word is 29 bits long. The serial interface works with
both a continuous and a burst (gated) serial clock. Serial data
applied to SDI is clocked into the AD5522 by clock pulses
applied to SCLK. The first falling edge of SYNC starts the write
cycle. At least 29 falling clock edges must be applied to SCLK to
clock in 29 bits of data, before SYNC is taken high again.
The input register addressed is updated on the rising edge of
SYNC . In order for another serial transfer to take place, SYNC
must be taken low again.
RESET FUNCTION
Bringing the level sensitive RESET line low resets the contents
of all internal registers to their power-on reset state (detailed in
CC
supply
Rev. PrM | Page 28 of 48
the section Power On Default). This sequence takes approx
300µs. The falling edge of RESET initiates the reset process;
BUSY goes low for the duration, returning high when RESET is
complete. While BUSY is low, all interfaces are disabled. When
BUSY returns high, normal operation resumes and the status of
the RESET pin is ignored until it goes low again. The SDO
output will be high impedance during a power on reset or a
RESET .
Power on reset follows the same function as RESET .
BUSY AND LOAD FUNCTION
BUSY is an open drain output that indicates the status of the
AD5522 interface. When writing to any of the registers BUSY
goes low and stays low until the command completes.
Writing to a DAC register drives the BUSY signal low for longer
than a simple PMU or System Control Register write. For the
DACs, the value of the internal cached (x2) data is calculated
and stored each time the user writes new data to the
corresponding x1 register. During this write and calculation, the
BUSY output is driven low. While BUSY is low, the user can
continue writing new data to the x1, m, or c registers, but no
output updates can take place.
X2 values are stored and held until a PMU word is written that
calls the appropriate cached x2 register. Only then does a DAC
output update.
The DAC outputs and PMU modes are updated by taking the
LOAD input low. If LOAD goes low while BUSY is active, the
LOAD event is stored and the DAC outputs or PMU modes
update immediately after BUSY goes high. A user can also hold
the LOAD input permanently low. In this case, the change in
DAC outputs or PMU modes update immediately after BUSY
goes high.
The BUSY pin is bidirectional and has a 50 kΩ internal pullup
resistor. Where multiple AD5522 devices may be used in one
system, the BUSY pins can be tied together. This is useful where
it is required that no DAC or PMU in any device is updated
until all others are ready. When each device has finished
updating the x2 registers, it will release the BUSY pin. If
another device has not finished updating its x2 registers, it will
hold BUSY low, thus delaying the effect of LOAD going low.
As there is only one multiplier shared between four channels,
this task must be done sequentially, so the length of the BUSY
pulse will vary according to the number of channels being
updated.
Preliminary Technical Data