AD5522JSVD AD [Analog Devices], AD5522JSVD Datasheet - Page 33

• Manufacturer Part Number: AD5522JSVD
• Description: Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
• Manufacturer: AD [Analog Devices]

B28
RD/ WR
Preliminary Technical Data
WRITE PMU REGISTER
To address PMU functions, set Mode bits MODE1, MODE0 low, this selects the PMU register as outlined in Table 13 and Table 14. The
AD5522 has very flexible addressing, in that it allows writing of data to a single PMU channel, any combination of them or all PMU
channels. This enables multi pin broadcasting to similar pins on a DUT. Bits 27 to 24 select which PMU or group of PMUs is addressed.
Table 17. PMU Register Bits
Table 18. PMU Register Functions
Bit
28
(MSB)
27
26
25
24
23
22
PMU REGISTER SPECIFIC BITS
21
20
19
18
17
16
15
B27
PMU3
B26
PMU2
Bit name
RD/ WR
PMU3
PMU2
PMU1
PMU0
MODE1
MODE0
CH EN
FORCE1
FORCE0
RESERVED
C2
C1
C0
B25
PMU1
B24
PMU0
Description
When low, a write function takes place to the selected register, while if the RD/ WR bit is set high, this initiates a readback
sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.
Bits PMU3 through PMU0 address each of the PMU channels in the device. This allows individual control of each PMU channel
or any manner of combined addressing in addition to multi-channel programming.
Mode Bits, MODE0 and MODE1 allow addressing of the PMU register or the DAC gain (m), offset (c ) or input register (x1). Set
to zero to access the PMU Register.
Channel Enable, Set high to enable the selected channel, similarly, set low to disable a selected channel or group of channels.
When disabled, SW 2 is closed, SW 5 open.
Bits FORCE1 and FORCE0 address the force function for each of the PMU channels (in association with P3-P0). All
combinations of forcing and measuring (using MEAS0 and MEAS1) are available. The Hi-Z (voltage and current) modes allows
user to optimize glitch response during mode changes. While in these modes, with PMU Hi-Z, new x1 codes loaded to the FIN
DAC register and the Clamp DAC register will be calibrated, stored in x2 register and loaded directly to the DAC outputs.
0
Bits C2 through C0 address allow selection of the required current range.
MODE1
B23
B27
PMU3
0
0
0
0
0
-
1
-
1
1
MODE1
0
0
1
1
FORCE1
0
0
1
1
C2
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
B22
MODE0
B26
PMU2
0
0
0
0
1
-
0
-
1
1
MODE0
0
1
0
1
FORCE0
0
1
0
1
C0
0
1
0
1
0
1
0
1
B21
CH
EN
Action
±5µA current range
±20µA current range
±200µA current range
±2mA current range
±external current range
Reserved
Reserved
Reserved
B25
PMU1
0
0
1
1
0
-
0
-
1
1
B20
FORCE1
Action
System Control Register or PMU Register
DAC Gain (m) Register
DAC Offset (c) Register
DAC Input Data Register, (x1)
Action
FV & Current Clamp (if clamp enabled)
FI & Voltage Clamp (if clamp enabled)
Hi-Z FOH Voltage (pre load FIN DAC & Clamp DAC)
Hi-Z FOH Current (pre load FIN DAC & Clamp DAC)
B24
PMU0
0
1
0
1
0
-
0
-
0
1
B19
FORCE0
Rev. PrM | Page 33 of 48
B23
MODE1
0
Select DAC or PMU Registers.
See below
B18
X
B17
C2
B16
C1
B22
MODE0
0
B15
C0
B14
MEAS1
B13
MEAS0
SELECTED REGISTER
CH3
Write to System Control Register
×
×
×
×
-
CH3
-
CH3
CH3
B12
FIN
CH2
×
×
×
CH2
-
×
-
CH2
CH2
B11
SF0
B10
SF0
CH1
×
CH1
CH1
×
-
×
-
CH1
CH1
B9
CL
CH0
CHO
×
CH0
×
-
×
-
×
CH0
B8
CPOLH
B7
COMPARE
V/I
AD5522
B6
CLEAR
B5 to B0
UNUSED
DATA
BITS