AD5522JSVD AD [Analog Devices], AD5522JSVD Datasheet - Page 37

• Manufacturer Part Number: AD5522JSVD
• Description: Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
READ REGISTERS
Readback of all the registers in the device is possible via the both SPI and LVDS interfaces. In order to readback data from a register, it is
first necessary to write a “readback” command to tell the device which register is required to readback. See Table 22 to address the
appropriate channel.
Once the required channel has been addressed, the device will load the 24 bit Readback data into the MSB positions of the 29 Bit serial
shift register, the five LSB bits will be filled with zeros. SCLK rising edges clock this readback data out on SDO(framed by the SYNC
signal).
A minimum of 24 clock rising edges are required to shift the readback data out of the shift register. If writing a 24-bit word to shift data
out of the device, user must ensure that the 24 bit write is effectively a NOP (No Operation) command. The last 5 bits in the shift register
will always be 00000b, these five bits will become the MSBs of the shift register when the 24 bit write is loaded. To ensure the device
receives a NOP command as outlined in Table 14, the recommended flush command is 0xFFFFFF and no change will be made to any
register within the device.
Readback data may also be shifted out by writing another 29 bit write or read command. If writing a 29-bit command, the readback data
will be MSB data available on SDO, followed by 00000b.
RD/WR
READ FUNCTIONS
READ ADDRESSED PMU REGISTER – ONLY ONE PMU REGISTER CAN BE READ AT ONE TIME
READ ADDRESSED DAC “m” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME
READ ADDRESSED DAC “c” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME
READ ADDRESSED DAC “x1” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME
B28
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PMU3
B27
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
PMU2
B26
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
PMU1
B25
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
PMU0
B24
Table 22. Read Functions of the AD5522
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
MODE1
B23
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Rev. PrM | Page 37 of 48
MODE0
B22
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DAC ADDRESS
SEE
DAC ADDRESS
DAC ADDRESS
SEE
SEE
DATA BITS
B21 to B0
All zeros
All zeros
All zeros
All zeros
Table 21
Table 21
Table 21
X
Read from System Control Register
Read from Comparator Status Registers
Reserved
Read from Alarm Status Register
CH3
CH3
CH3
CH3
CH3
×
×
×
×
×
×
×
×
×
×
×
×
SELECTED REGISTER
CH2
CH2
CH2
CH2
CH2
×
×
×
×
×
×
×
×
×
×
×
×
CH1
CH1
CH1
CH1
CH1
×
×
×
×
×
×
×
×
×
×
×
×
CH0
CH0
CH0
CH0
CH0
×
×
×
×
×
×
×
×
×
×
×
×
AD5522