SC16C2550B_07 PHILIPS [NXP Semiconductors], SC16C2550B_07 Datasheet - Page 13

• Manufacturer Part Number: SC16C2550B_07
• Description: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
SC16C2550B_4
Product data sheet
6.6 DMA operation
6.7 Loop-back mode
Table 7.
The SC16C2550B FIFO trigger level provides additional flexibility to the user for block
mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an
empty location(s). The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC16C2550B activates the interrupt output pin
for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1),
the user takes the advantage of block mode operation by loading or unloading the FIFO in
a block sequence determined by the receive trigger level and the transmit FIFO. In this
mode, the SC16C2550B sets the TXRDY (or RXRDY) output pin when characters in the
transmit FIFO is below 16 or the characters in the receive FIFOs are above the receive
trigger level.
The internal loop-back capability allows on-board diagnostics. In the Loop-back mode, the
normal modem interface pins are disconnected and reconfigured for loop-back internally
(see
In the Loop-back mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins and instead are connected together
internally. The CTS, DSR, CD and RI are disconnected from their normal modem control
inputs pins and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2]
(OP1). Loop-back test data is entered into the transmit holding register via the user data
bus interface, D0 through D7. The transmit UART serializes the data and passes the serial
data to the receive UART via the internal loop-back connection. The receive UART
Output
baud rate
(bit/s)
50
75
110
150
300
600
1200
2400
3600
4800
7200
9600
19.2 k
38.4 k
57.6 k
115.2 k
Figure
Baud rate generator programming table using a 1.8432 MHz clock
7). MCR[0:3] register bits are used for controlling loop-back diagnostic testing.
Output
16 clock divisor
(decimal)
2304
1536
1047
768
384
192
96
48
32
24
16
12
6
3
2
1
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 04 — 15 February 2007
Output
16 clock divisor
(hexadecimal)
900
600
417
300
180
C0
60
30
20
18
10
0C
06
03
02
01
DLM
program value
(hexadecimal)
09
06
04
03
01
00
00
00
00
00
00
00
00
00
00
00
SC16C2550B
© NXP B.V. 2007. All rights reserved.
DLL
program value
(hexadecimal)
00
00
17
00
80
C0
60
30
20
18
10
0C
06
03
02
01
13 of 43