SC16C2550B_07 PHILIPS [NXP Semiconductors], SC16C2550B_07 Datasheet - Page 17

• Manufacturer Part Number: SC16C2550B_07
• Description: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
SC16C2550B_4
Product data sheet
7.3.1.1 Mode 0 (FCR bit 3 = 0)
7.3.1.2 Mode 1 (FCR bit 3 = 1)
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
7.3.1 DMA mode
7.3 FIFO Control Register (FCR)
When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reflect the following:
When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C2550B in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll the
LSR register for TX and/or RX data status. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels and select the DMA mode.
Set and enable the interrupt for each single transmit or receive operation and is similar to
the 16C450 mode. Transmit Ready (TXRDY) on PLCC44 and LQFP48 packages will go to
a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive Ready
(RXRDY) on PLCC44 and LQFP48 packages will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is empty. TXRDY on PLCC44 and LQFP48 packages remains a logic 0
as long as one empty FIFO location is available. The receive interrupt is set when the
receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
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The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit and
the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR[0]) is set as soon as a character is transferred from
the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.
When the Transmit FIFO and interrupts are enabled, an interrupt is generated when
the transmit FIFO is empty due to the unloading of the data by the TSR and UART for
transmission via the transmission media. The interrupt is cleared either by reading the
ISR register or by loading the THR with new data characters.
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of receive errors or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will show if any FIFO data errors occurred.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 04 — 15 February 2007
SC16C2550B
© NXP B.V. 2007. All rights reserved.
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