SC16C2550B_07 PHILIPS [NXP Semiconductors], SC16C2550B_07 Datasheet - Page 18

• Manufacturer Part Number: SC16C2550B_07
• Description: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
SC16C2550B_4
Product data sheet
7.3.2 FIFO mode
regardless of the programmed level until the FIFO is full. RXRDY on PLCC44 and
LQFP48 packages transitions LOW when the FIFO reaches the trigger level and
transitions HIGH when the FIFO empties.
Table 10.
Bit
7:6
5:4
3
2
Symbol
FCR[7:6]
FCR[5:4]
FCR[3]
FCR[2]
FIFO Control Register bits description
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 04 — 15 February 2007
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to be
loaded until it is full. Refer to
Not used; initialized to logic 0.
DMA mode select.
Transmit operation in mode ‘0’: When the SC16C2550B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0) and when there are no
characters in the transmit FIFO or Transmit Holding Register, the TXRDY
pin in PLCC44 or LQFP48 packages will be a logic 0. Once active, the
TXRDY pin will go to a logic 1 after the first character is loaded into the
Transmit Holding Register.
Receive operation in mode ‘0’: When the SC16C2550B is in mode ‘0’
(FCR[0] = logic 0) or in the FIFO mode (FCR[3] = logic 0) and there is at
least one character in the receive FIFO, the RXRDY pin will be a logic 0.
Once active, the RXRDY pin on PLCC44 and LQFP48 packages will go to
a logic 1 when there are no more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C2550B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin on PLCC44 and
LQFP48 packages will be a logic 1 when the transmit FIFO is completely
full. It will be a logic 0 if one or more FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C2550B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached
or a Receive Time-out has occurred, the RXRDY pin on PLCC44 and
LQFP48 packages will go to a logic 0. Once activated, it will go to a logic 1
after there are no more characters in the FIFO.
XMIT FIFO reset.
logic 0 (or cleared) = normal default condition
logic 1 = RX trigger level
logic 0 = set DMA mode ‘0’
logic 1 = set DMA mode ‘1’
logic 0 = Transmit FIFO not reset (normal default condition).
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the Transmit Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
Table
11.
SC16C2550B
© NXP B.V. 2007. All rights reserved.
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