SC16C2550B_07 PHILIPS [NXP Semiconductors], SC16C2550B_07 Datasheet - Page 7

• Manufacturer Part Number: SC16C2550B_07
• Description: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
Table 3.
SC16C2550B_4
Product data sheet
Symbol
RESET
RXRDYA -
RXRDYB -
TXRDYA
TXRDYB -
V
XTAL1
XTAL2
CDA
CDB
CTSA
CTSB
CC
Pin
HVQFN32 DIP40 PLCC44 LQFP48
24
-
26
10
11
-
-
25
16
Pin description
35
-
-
-
-
40
16
17
38
19
36
25
…continued
39
34
23
1
12
44
18
19
42
21
40
28
36
31
18
43
6
42
13
14
40
16
38
23
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 04 — 15 February 2007
Type
I
O
O
O
O
I
I
O
I
I
I
I
Description
Reset (active HIGH). A logic 1 on this pin will reset the internal
registers and all the outputs. The UART transmitter output and
the receiver input will be disabled during reset time. (See
Section 7.10 “SC16C2550B external reset condition”
initialization details.)
Receive Ready A, B (active LOW). This function is associated
with PLCC44 and LQFP48 packages only. This function
provides the RX FIFO/RHR status for individual receive
channels (A-B). RXRDYn is primarily intended for monitoring
DMA mode 1 transfers for the receive data FIFOs. A logic 0
indicates there is a receive data to read/upload, that is, receive
ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty
or when the programmed trigger level has not been reached.
This signal can also be used for single mode transfers (DMA
mode 0).
Transmit Ready A, B (active LOW). This function is
associated with PLCC44 and LQFP48 packages only. These
outputs provide the TX FIFO/THR status for individual transmit
channels (A, B). TXRDYn is primarily intended for monitoring
DMA mode 1 transfers for the transmit data FIFOs. An
individual channel’s TXRDYA, TXRDYB buffer ready status is
indicated by logic 0, that is, at least one location is empty and
available in the FIFO or THR. This pin goes to a logic 1 (DMA
mode 1) when there are no more empty locations in the FIFO
or THR. This signal can also be used for single mode transfers
(DMA mode 0).
Power supply input.
Crystal or external clock input. Functions as a crystal input
or as an external clock input. A crystal can be connected
between this pin and XTAL2 to form an internal oscillator
circuit. Alternatively, an external clock can be connected to this
pin to provide custom data rates. (See
“Programmable baud rate
Output of the crystal oscillator or buffered clock. (See also
XTAL1.) Crystal oscillator output or buffered clock output.
Should be left open if an external clock is connected to XTAL1.
For extended frequency operation, this pin should be tied to
V
Carrier Detect (active LOW). These inputs are associated
with individual UART channels A through B. A logic 0 on this
pin indicates that a carrier has been detected by the modem for
that channel.
Clear to Send (active LOW). These inputs are associated with
individual UART channels, A through B. A logic 0 on the CTS
pin indicates the modem or data set is ready to accept transmit
data from the SC16C2550B. Status can be tested by reading
MSR[4]. This pin has no effect on the UART’s transmit or
receive operation.
CC
via a 2 k resistor.
generator”.) See
SC16C2550B
Section 6.5
© NXP B.V. 2007. All rights reserved.
Figure
6.
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