SC16C554BIB64 PHILIPS [NXP Semiconductors], SC16C554BIB64 Datasheet - Page 23

• Manufacturer Part Number: SC16C554BIB64
• Description: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
7. Register descriptions
Table 9:
[1]
[2]
[3]
9397 750 13133
Product data sheet
A2 A1 A0 Register Default
General Register set
0
0
0
0
0
0
1
1
1
1
Special Register set
0
0
The value shown represents the register’s initialized HEX value; X = not applicable.
These registers are accessible only when LCR[7] = 0.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
SC16C554B/554DB internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
[3]
[2]
Table 9
The assigned bit functions are more fully defined in
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
details the assigned bit functions for the SC16C554B/554DB internal registers.
[1]
Bit 7
bit 7
bit 7
0
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
CD
bit 7
bit 7
bit 15
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Bit 6
bit 6
bit 6
0
RCVR
trigger
(LSB)
FIFOs
enabled
set
break
0
trans.
empty
RI
bit 6
bit 6
bit 14
Rev. 01 — 9 February 2005
Bit 5
bit 5
bit 5
0
reserved reserved
0
set
parity
autoflow
control
enable
trans.
holding
empty
DSR
bit 5
bit 5
bit 13
Bit 4
bit 4
bit 4
0
0
even
parity
loop back OP2,
break
interrupt
CTS
bit 4
bit 4
bit 12
SC16C554B/554DB
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
INTx
enable
framing
error
bit 3
bit 3
bit 11
Section 7.1
CD
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Bit 2
bit 2
bit 2
receive
line status
interrupt
XMIT
FIFO reset
INT
priority
bit 1
stop bits
OP1
parity
error
bit 2
bit 2
bit 10
RI
through
Bit 1
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
Section
DSR
7.10.
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
CTS
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