SC16C554BIB64 PHILIPS [NXP Semiconductors], SC16C554BIB64 Datasheet - Page 24

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SC16C554BIB64

Manufacturer Part Number
SC16C554BIB64
Description
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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Product data sheet
7.1 Transmit (THR) and Receive (RHR) Holding Registers
7.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C554B/554DB and receive FIFO by reading the
RHR register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting clocks
at the 16 clock rate. After 7
the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA to INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the
68 mode.
Table 10:
Bit
7:4
3
2
1
0
Symbol
IER[7:4]
IER[3]
IER[2]
IER[1]
IER[0]
Interrupt Enable Register bits description
Description
Reserved; set to ‘0’.
Modem Status Interrupt.
Receive Line Status interrupt.
Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
Receive Holding Register interrupt. This interrupt will be issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
Logic 0 = Disable the receiver line status interrupt (normal default condition).
Logic 1 = Enable the receiver line status interrupt.
Logic 0 = Disable the transmitter empty interrupt (normal default condition).
Logic 1 = Enable the transmitter empty interrupt.
Logic 0 = Disable the receiver ready interrupt (normal default condition).
Logic 1 = Enable the receiver ready interrupt.
Rev. 01 — 9 February 2005
1
2
clocks, the start bit time should be shifted to the center of
SC16C554B/554DB
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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