SC16C654BIB64 PHILIPS [NXP Semiconductors], SC16C654BIB64 Datasheet

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SC16C654BIB64

Manufacturer Part Number
SC16C654BIB64
Description
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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1. General description
2. Features
The SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmitter
(QUART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
It comes with an Intel or Motorola interface.
The SC16C654B/654DB is pin compatible with the ST16C654 and TL16C754 and it will
power-up to be functionally equivalent to the 16C454. Programming of control registers
enables the added features of the SC16C654B/654DB. Some of these added features are
the 64-byte receive and transmit FIFOs, automatic hardware or software flow control and
infrared encoding/decoding. The selectable auto-flow control feature significantly reduces
software overload and increases system efficiency while in FIFO mode by automatically
controlling serial data flow using RTS output and CTS input signals. The
SC16C654B/654DB also provides DMA mode data transfers through FIFO trigger levels
and the TXRDY and RXRDY signals. (TXRDY and RXRDY signals are not available in the
HVQFN48 package.) On-board status registers provide the user with error indications,
operational status, and modem interface control. System interrupts may be tailored to
meet user requirements. An internal loop-back capability allows on-board diagnostics.
The SC16C654B/654DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, HVQFN48 and LFBGA64 packages.
On the HVQFN48 package, only channel C has all the modem pins. Channel A and
channel B have only RTS and CTS pins, and channel D does not have any modem pin.
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte
FIFOs and infrared (IrDA) encoder/decoder
Rev. 02 — 20 June 2005
4 channel UART
5 V, 3.3 V and 2.5 V operation
Industrial temperature range ( 40 C to +85 C)
SC16C654B is pin and software compatible with the industry-standard
ST16C454/554, ST16C654, ST68C454/554, TL16C554
SC16C654DB is pin and software compatible with ST16C654D, and software
compatible with ST16C454/554, ST68C454/554, TL16C554
Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V
5 V tolerant inputs
64-byte transmit FIFO
64-byte receive FIFO with error flags
Automatic software (Xon/Xoff)/hardware (RTS/CTS) flow control
Programmable Xon/Xoff characters
Product data sheet

Related parts for SC16C654BIB64

SC16C654BIB64 Summary of contents

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SC16C654B/654DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder Rev. 02 — 20 June 2005 1. General description The SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmitter (QUART) ...

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... Loop-back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, CD). 3. Ordering information Table 1: Ordering information Type number Package Name SC16C654BIA68 PLCC68 SC16C654BIB64 LQFP64 SC16C654BIBM LQFP64 SC16C654BIBS HVQFN48 SC16C654BIEC LFBGA64 SC16C654DBIB64 LQFP64 9397 750 14965 Product data sheet ...

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Philips Semiconductors 4. Block diagram SC16C654B/654DB DATA BUS IOR AND IOW CONTROL RESET LOGIC REGISTER SELECT CSA to CSD LOGIC 16/68 INTA to INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC INTSEL Fig 1. Block diagram ...

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Philips Semiconductors SC16C654B/654DB DATA BUS AND R/W CONTROL RESET LOGIC REGISTER SELECT CS LOGIC 16/68 IRQ INTERRUPT TXRDY CONTROL RXRDY LOGIC Fig 2. Block diagram of SC16C654B/654DB (68 mode) 9397 750 14965 Product data ...

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Philips Semiconductors 5. Pinning information 5.1 Pinning Fig 3. Pin configuration for PLCC68 (16 mode) 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs 10 DSRA CTSA 11 ...

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Philips Semiconductors Fig 4. Pin configuration for PLCC68 (68 mode) 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs DSRA 10 CTSA 11 12 DTRA ...

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... Fig 5. Pin configuration for LQFP64 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs DSRA 1 2 CTSA DTRA RTSA 5 6 INTA CSA 7 SC16C654BIB64 TXA 8 SC16C654BIBM 9 IOW SC16C654DBIB64 TXB 10 CSB 11 INTB 12 13 RTSB GND 14 DTRB 15 ...

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Philips Semiconductors Fig 6. Pin configuration for HVQFN48 (16 mode) Fig 7. Pin configuration for HVQFN48 (68 mode) 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs terminal ...

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Philips Semiconductors Fig 8. Pin configuration for LFBGA64 Fig 9. Ball mapping for LFBGA64 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 ...

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Philips Semiconductors 5.2 Pin description Table 2: Pin description Symbol Pin PLCC68 LQFP64 HVQFN48 LFBGA6 16/ CDA ...

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Philips Semiconductors Table 2: Pin description …continued Symbol Pin PLCC68 LQFP64 HVQFN48 LFBGA6 CSA CSB CSC CSD CTSA CTSB CTSC 45 33 ...

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... Due to pin limitations on the 64-pin packages, this pin is not available. To cover this limitation, the SC16C654DBIB64 version operates in the continuous interrupt enable mode by bonding this pin to V internally. The SC16C654BIB64 operates with MCR[3] control by bonding this pin to GND Input/Output Read strobe (active LOW) ...

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Philips Semiconductors Table 2: Pin description …continued Symbol Pin PLCC68 LQFP64 HVQFN48 LFBGA6 RIA RIB RIC RID RTSA RTSB RTSC 48 36 ...

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Philips Semiconductors Table 2: Pin description …continued Symbol Pin PLCC68 LQFP64 HVQFN48 LFBGA6 TXRDY 13, 47 35, 52 XTAL1 XTAL2 Functional description The ...

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Philips Semiconductors time. In addition, the four selectable levels of FIFO trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance, especially when operating in a multi-channel environment. The combination of the above greatly reduces ...

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Philips Semiconductors 6.1 Interface options Two user interface modes are selectable for the PLCC68 package. These interface modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature corresponds to the early 16C454/554 and 68C454/554 package interfaces respectively. ...

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Philips Semiconductors 6.2 Internal registers The SC16C654B/654DB provides 17 internal registers for monitoring and control. These registers are shown in the standard 16C554. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control ...

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Philips Semiconductors Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. (For a description of this timing, see 6.4 “Hardware flow Table 6: Selected trigger level (characters) ...

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Philips Semiconductors Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff ...

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Philips Semiconductors When two interrupt conditions have the same priority important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after ...

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Philips Semiconductors SC16C654B/654DB sets the default baud rate table according to the state of the CLKSEL pin. A logic 1 on CLKSEL will set the 1 clock default, whereas logic 0 will set the 4 clock default table. Following the ...

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Philips Semiconductors 6.10 DMA operation The SC16C654B/654DB FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[5:6] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the ...

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Philips Semiconductors SC16C654B/654DB DATA BUS IOR AND IOW CONTROL RESET LOGIC REGISTER SELECT CSA to CSD LOGIC INTA to INTD INTERRUPT TXRDY CONTROL RXRDY LOGIC Fig 12. Internal loop-back mode diagram 9397 750 14965 ...

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Philips Semiconductors 7. Register descriptions Table 8 The assigned bit functions are more fully defined in Table 8: SC16C654B/654DB internal registers [ Register Default [2] General Register Set RHR THR ...

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Philips Semiconductors 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). ...

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Philips Semiconductors Table 9: Bit Symbol 2 IER[2] 1 IER[1] 0 IER[0] 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts ...

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Philips Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit ...

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Philips Semiconductors Table 10: Bit 3 (cont Table 11: FCR[ Table 12: FCR[ 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 ...

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Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C654B/654DB provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR ...

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Philips Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this ...

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Philips Semiconductors Table 16: LCR[ Table 17: LCR[ Table 18: LCR[ 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. ...

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Philips Semiconductors Table 19: Bit 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs Modem Control Register bits description Symbol Description MCR[4] Loop-back. ...

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Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C654B/654DB and the CPU. Table 20: Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 ...

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Philips Semiconductors 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C654B/654DB is connected. Four bits of this register are used to indicate ...

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Philips Semiconductors 7.9 Scratchpad Register (SPR) The SC16C654B/654DB provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single ...

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Philips Semiconductors Table 23: Cont [1] When using software flow control the Xon/Xoff characters cannot be used for data transfer. 7.11 SC16C654B/654DB external reset conditions Table 24: Register IER ISR ...

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Philips Semiconductors 8. Limiting values Table 26: In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg P tot(pack) 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 ...

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Table 27: Static characteristics +85 C; tolerance unless otherwise specified. amb CC Symbol Parameter Conditions V LOW-level clock input voltage IL(CK) V HIGH-level clock input voltage IH(CK) V LOW-level input ...

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Philips Semiconductors 10. Dynamic characteristics Table 28: Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter clock pulse duration oscillator/clock frequency XTAL t address setup time 6s t ...

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Philips Semiconductors Table 28: Dynamic characteristics +85 C; tolerance of V amb Symbol Parameter t delay from start to reset 28d TXRDY t address setup time 30s t chip select strobe width 30w t address ...

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Philips Semiconductors 10.1 Timing diagrams 30s CS t 32s R Fig 13. General read timing in 68 mode 30s CS t 32s R Fig 14. General ...

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Philips Semiconductors IOW Fig 15. General write timing in 16 mode IOR Fig 16. General read timing in 16 mode 9397 750 ...

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Philips Semiconductors active IOW RTS change of state DTR CD CTS DSR INT IOR RI Fig 17. Modem input/output timing EXTERNAL CLOCK ------- XTAL t 3w Fig 18. External clock timing 9397 750 14965 Product data sheet ...

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Philips Semiconductors RX INT IOR Fig 19. Receive timing RX RXRDY IOR Fig 20. Receive ready timing in non-FIFO mode 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte ...

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Philips Semiconductors RX RXRDY IOR Fig 21. Receive ready timing in FIFO mode TX INT active IOW Fig 22. Transmit timing 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with ...

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Philips Semiconductors TX IOW active byte #1 t 27d TXRDY Fig 23. Transmit ready timing in non-FIFO mode TX IOW active byte #16 TXRDY Fig 24. Transmit ready timing in FIFO mode (DMA mode ...

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Philips Semiconductors TX data IrDA TX data Fig 25. Infrared transmit timing IrDA RX data RX data Fig 26. Infrared receive timing 9397 750 14965 Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) ...

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Philips Semiconductors 11. Package outline PLCC68: plastic leaded chip carrier; 68 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT A ...

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Philips Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT ...

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Philips Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT ...

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Philips Semiconductors HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm ...

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Philips Semiconductors LFBGA64: plastic low profile fine-pitch ball grid array package; 64 balls; body 1.05 mm ball A1 index area ball ...

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Philips Semiconductors 12. Soldering 12.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...

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Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...

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Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...

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Philips Semiconductors 14. Revision history Table 31: Revision history Document ID Release date SC16C654B_654DB_2 20050620 • Modifications: Section 1 “General – 2nd paragraph: added 6th sentence. – 3rd paragraph: added HVQFN48 and LFBGA64 package options, and added second • Table ...

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Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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Philips Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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