SC16C850IBS NXP [NXP Semiconductors], SC16C850IBS Datasheet
SC16C850IBS
Available stocks
Related parts for SC16C850IBS
SC16C850IBS Summary of contents
Page 1
... System interrupts and modem control features may be tailored by software to meet specific user requirements. An internal loopback capability allows on-board diagnostics. The SC16C850IBS with Intel (16 mode) or Motorola (68 mode) bus host interface operates at 2 3.3 V and is available in a very small (Micro-UART) HVQFN32 package. ...
Page 2
... Modem control functions (CTS, RTS, DSR, DTR, RI, CD) I Independent transmitter and receiver enable/disable I Pb-free, RoHS compliant package offered 3. Ordering information Table 1. Type number SC16C850IBS SC16C850IET SC16C850_1 Product data sheet 2 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder Ordering information Package Name ...
Page 3
NXP Semiconductors 4. Block diagram SC16C850 DATA BUS IOR IOW CONTROL RESET REGISTER SELECT CS POWER-DOWN LOWPWR CONTROL INTERRUPT INT CONTROL Fig 1. Block diagram of SC16C850 (16 mode) SC16C850_1 Product data sheet 2.5 ...
Page 4
NXP Semiconductors SC16C850 DATA BUS R/W CONTROL RESET REGISTER SELECT CS POWER-DOWN LOWPWR CONTROL INTERRUPT IRQ CONTROL Fig 2. Block diagram of SC16C850 (68 mode) SC16C850_1 Product data sheet 2 3.3 V ...
Page 5
NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 3. Pin configuration for TFBGA36 Fig 4. Ball mapping for TFBGA36 SC16C850_1 Product data sheet 2 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder ball A1 index area A ...
Page 6
... Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. Rev. 01 — 10 January 2008 SC16C850 SC16C850IBS 21 (68 mode Transparent top view © ...
Page 7
NXP Semiconductors Table 2. Pin description …continued Symbol Pin TFBGA36 HVQFN32 INT - 20 (IRQ) INT ...
Page 8
NXP Semiconductors Table 2. Pin description …continued Symbol Pin TFBGA36 HVQFN32 RTS A1 [ XTAL1 A6 10 XTAL2 A5 11 [1] HVQFN package ...
Page 9
NXP Semiconductors 6. Functional description The SC16C850 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is ...
Page 10
NXP Semiconductors Table HIGH LOW. Chip Select 6.2 Extended mode (128-byte FIFO) The device is in the extended mode when any of these four registers contains any value other ...
Page 11
NXP Semiconductors Table Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1 [1] These registers are accessible only when LCR[ logic 0. [2] These registers are accessible ...
Page 12
NXP Semiconductors 6.5 Hardware flow control When automatic hardware flow control is enabled, the SC16C850 monitors the CTS pin for a remote buffer overflow indication and controls the RTS pin for local buffer overflows. Automatic hardware flow control is selected ...
Page 13
NXP Semiconductors Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset, the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff ...
Page 14
NXP Semiconductors each time the Receive Holding Register (RHR) is read. The actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, that is 1 ...
Page 15
NXP Semiconductors Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in shows the selectable baud rate table available when using a 1.8432 MHz ...
Page 16
NXP Semiconductors Table 7. Output baud rate (bit/s) 38.4 k 57.6 k 115.2 k 6.10 Loopback mode The internal loopback capability allows on-board diagnostics. In the Loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally ...
Page 17
NXP Semiconductors SC16C850 DATA BUS AND IOR CONTROL IOW LOGIC RESET REGISTER SELECT CS LOGIC POWER- LOWPWR DOWN CONTROL INTERRUPT INT CONTROL (IRQ) LOGIC Fig 9. Internal Loopback mode diagram SC16C850_1 Product data sheet ...
Page 18
NXP Semiconductors 6.11 Sleep mode Sleep mode is an enhanced feature of the SC16C850 UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] bit is set. 6.11.1 Conditions to enter Sleep mode Sleep mode ...
Page 19
NXP Semiconductors 6.13 RS-485 features 6.13.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR[1 hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. ...
Page 20
NXP Semiconductors 6.13.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the Xoff2 register contains the address byte) the receiver will try to detect an address byte that matches the programmed character in the Xoff2 ...
Page 21
Table 8. SC16C850 internal registers [ Register Default Bit 7 [2] General register set RHR 0xXX bit THR 0xXX bit IER 0x00 CTS [3] interrupt 0 ...
Page 22
Table 8. SC16C850 internal registers …continued [ Register Default Bit 7 [5] Enhanced feature register set EFR 0x00 Auto CTS Xon1 0x00 bit Xon2 0x00 bit 15 ...
Page 23
NXP Semiconductors 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). ...
Page 24
NXP Semiconductors Table 9. Bit Symbol Description 1 IER[1] 0 IER[0] 7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation When the receive FIFO is enabled (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive ...
Page 25
NXP Semiconductors 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO trigger levels. 7.3.1 FIFO mode Table 10. Bit 7:6 5 [1] For 128-byte ...
Page 26
NXP Semiconductors Table 12. FCR[ [1] When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see 7.4 Interrupt Status Register (ISR) The ...
Page 27
NXP Semiconductors Table 14. Bit 0 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the ...
Page 28
NXP Semiconductors Table 18. LCR[ 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19. Bit SC16C850_1 Product data ...
Page 29
NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C850 and the CPU. Table 20. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 ...
Page 30
NXP Semiconductors 7.8 Modem Status Register (MSR) This register shares the same address as EFCR register. This is a read-only register and it provides the current state of the control interface signals from the modem, or other peripheral device to ...
Page 31
NXP Semiconductors 7.9 Extra Feature Control Register (EFCR) This is a write-only register, and it allows the software access to these registers: ‘first extra feature register set’, ‘second extra feature register set’, Transmit FIFO Level Counter (TXLVLCNT), and Receive FIFO ...
Page 32
NXP Semiconductors 7.14 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are ...
Page 33
NXP Semiconductors Table 24. Cont [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.15 Transmit Interrupt Level Register (TXINTLVL) This 8-bit register ...
Page 34
NXP Semiconductors [1] For 32-byte FIFO mode, refer to 7.17 Flow Control Trigger Level High (FLWCNTH) This 8-bit register is used to store the receive FIFO high threshold levels to start/stop transmission during hardware/software flow control. register bit settings; see ...
Page 35
NXP Semiconductors 7.20 RS-485 Turn-around time delay (RS485TIME) The value in this register controls the turn-around time of the external line transceiver in bit time. In automatic 9-bit mode RTS or DTR pin is used to control the direction of ...
Page 36
NXP Semiconductors 7.22 Advanced Feature Control Register 1 (AFCR1) Table 32. Bit 7 [1] It takes 4 XTAL1 clocks to reset the device. SC16C850_1 Product data sheet 2 3.3 V UART with 128-byte ...
Page 37
NXP Semiconductors 7.23 SC16C850 external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 33. Table 33. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL ...
Page 38
NXP Semiconductors 8. Limiting values Table 35. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg P /pack tot 9. Static characteristics Table 36. Static characteristics ...
Page 39
NXP Semiconductors 10. Dynamic characteristics Table 37. Dynamic characteristics - Intel or 16 mode +85 C; tolerance of V amb Symbol Parameter t pulse width HIGH WH t pulse width LOW WL t clock pulse ...
Page 40
NXP Semiconductors Table 38. Dynamic characteristics - Motorola or 68 mode +85 C; tolerance of V amb Symbol Parameter t pulse width HIGH WH t pulse width LOW WL t clock pulse width w(clk) f ...
Page 41
NXP Semiconductors 10.1 Timing diagrams su( d(CSL-IOWL) IOW Fig 10. General write timing (16 mode su( su(RWL-CSL) R Fig 11. General write ...
Page 42
NXP Semiconductors su( d(CS-IOR) IOR Fig 12. General read timing (16 mode su( su(RWH-CSL) R Fig 13. General read timing (68 mode) ...
Page 43
NXP Semiconductors active IOW RTS change of state DTR CD CTS DSR INT IOR RI Fig 15. Modem input/output timing (16 mode) (1) CS (write) RTS change of state DTR CD CTS DSR IRQ (2) CS (read) RI (1) CS ...
Page 44
NXP Semiconductors RX (1)(2) INT IOR (1) INT is active when RX FIFO fills up to trigger level or a time-out condition happens (see (2) INT is cleared when RX FIFO drops below trigger level. Fig 17. Receive timing in ...
Page 45
NXP Semiconductors TX (1)(2) INT active IOW (1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level. (2) INT is cleared when ISR is read or TX FIFO fills up to trigger level. Fig ...
Page 46
NXP Semiconductors TX data IrDA TX data Fig 21. Infrared transmit timing IrDA RX data RX data Fig 22. Infrared receive timing SC16C850_1 Product data sheet 2 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder UART frame ...
Page 47
NXP Semiconductors 11. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area ...
Page 48
NXP Semiconductors TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball A1 1 index area DIMENSIONS (mm are ...
Page 49
NXP Semiconductors 12. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering ...
Page 50
NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
Page 51
NXP Semiconductors Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Abbreviations Table 41. Acronym CPU DLL DLM FIFO IrDA ISDN LSB ...
Page 52
NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
Page 53
NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...