TFA9812HN PHILIPS [NXP Semiconductors], TFA9812HN Datasheet

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TFA9812HN

Manufacturer Part Number
TFA9812HN
Description
BTL stereo Class-D audio amplifier with I2S input
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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Part Number:
TFA9812HN/N1,518
Manufacturer:
NXP USA Inc.
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1. General description
2. Features
2.1 General features
The TFA9812 is a high-efficiency Bridge Tied Load (BTL) stereo Class-D audio amplifier
with a digital I
paddle. The exposed die paddle technology enhances the thermal and electrical
performances of the device.
The TFA9812 features digital sound processing and audio power amplification. It supports
I
because the key features are controlled by hardware pin connections.
A continuous time output power of 2
an external heat sink. Due to the implementation of a programmable thermal foldback
even for high supply voltages, higher ambient temperatures, and/or lower load
impedances, the device operates without sound interrupting behavior.
TFA9812 is designed in such a way that it starts up easily (no special power-up sequence
required). It features various soft and hard impact protection mechanisms to ensure an
application that is both user friendly and robust.
A modulation technique is applied for the TFA9812, which supports common mode choke
approach (1 common mode choke only per BTL amplifier stage). This minimizes the
number of external components.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
C control mode and Legacy mode. In Legacy mode I
TFA9812
BTL stereo Class-D audio amplifier with I
Rev. 02 — 22 January 2009
3.3 V and 8 V to 20 V external power supply
High efficiency and low power dissipation
Speaker outputs fully short circuit proof across load, to supply lines and ground
Pop noise free at power-up/power-down and sample rate switching
Low power Sleep mode
Overvoltage and undervoltage protection on the 8 V to 20 V power supply
Undervoltage protection on the 3.3 V power supply
Overcurrent protection (no audible interruptions)
Overdissipation protection
Thermally protected and programmable thermal foldback
Clock error protection
I
Four different I
Internal Phase-Locked Loop (PLL) without using external components
2
C mode control or Legacy mode (i.e. no I
2
S audio input. It is available in a HVQFN48 package with exposed die
2
C addresses supported
12 W (R
2
L
C) control
= 8 , V
2
C involvement is not needed
DDP
2
= 15 V) is supported without
S input
Preliminary data sheet

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TFA9812HN Summary of contents

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TFA9812 BTL stereo Class-D audio amplifier with I Rev. 02 — 22 January 2009 1. General description The TFA9812 is a high-efficiency Bridge Tied Load (BTL) stereo Class-D audio amplifier with a digital I paddle. The exposed die paddle technology ...

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NXP Semiconductors I No high system clock required (PLL is able to lock on BCK external heat sink required tolerant digital inputs I Supports dual coil inductor application I Easy application and limited external components ...

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NXP Semiconductors 4. Quick reference data Table 1. Unless specified otherwise SS1 2 24-bit I S input data, MCLK clock mode, typical application diagram Symbol General V DDA V DDP V DDA(3V3) V DDD(3V3 ...

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... NXP Semiconductors 5. Ordering information Table 2. Ordering information Type number Package Name TFA9812HN HVQFN48 TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Description plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 7 0.85 mm Rev. 02 — 22 January 2009 ...

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Block diagram TEST1 TEST2 7 43 PHASED REGISTER LOCKED ADDRESS LOOP HEX 01 XTALIN 1 CLOCK OSCILLATOR PROTECTION XTALOUT 2 LP UFP MCLK 47 OFP IBP BCK 46 VOLUME SERIAL 10-BAND WS 45 CONTROL AUDIO PARAMETRIC AND SOFT DATA ...

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... TFA9812. For a detailed description of the audio Section 8.1. terminal 1 index area XTALIN 1 XTALOUT DDA(3V3) 4 STABA REFA DDA TFA9812HN 7 TEST1 8 V SS1 STAB2 SSP2 11 V SSP2 BOOT2N 12 Transparent top view Pin configuration, transparent top view Pinning description TFA9812 ...

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NXP Semiconductors Table 3. Pin TFA9812_2 Preliminary ...

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NXP Semiconductors Table 3. Pin 47 48 Exposed die-paddle 8. Functional description 8.1 General The TFA9812 is a high-efficiency stereo BTL Class-D amplifier with a digital I input. It supports all commonly used I Figure 1 TFA9812. In the digital ...

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NXP Semiconductors The block control defines the operational control settings of the TFA9812 in line with the actual I The PLL block creates the system clock and can take the I external crystal as reference source. The following protections are ...

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NXP Semiconductors • In Soft mute mode the I – In Legacy control mode the analog input pin AVOL controls Soft mute mode. – function. See also • In Hard mute mode the PWM controller is overruled with ...

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NXP Semiconductors Table 6. Pin value CSEL [1] Under these conditions the mode is enabled by the appropriate slave mode selection between BCK and MCLK clock modes is automatic. MCLK clock mode ...

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NXP Semiconductors Table 8. Control mode Legacy Table 9. Control mode Legacy [1] The valid sample frequencies are shown in TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I 2 Valid MCLK frequencies in I ...

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NXP Semiconductors 8.3 Power-up/power-down external voltage supplies POWERUP ENABLE available soft mute setting mode AVOL pin in Legacy mode PWM outputs Operating mode active Fig 3. 8.3.1 Power-up Figure 3 for initiating a power-up reset. Table ...

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NXP Semiconductors control mode communication is enabled after 4 ms. The preferred I be made within 66 ms before the PLL starts running. Finally, the output stages are enabled and the audio level is increased via ...

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NXP Semiconductors Table 12. BCK frequency Interface format (MSB first ...

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NXP Semiconductors control mode the following sample frequency f 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz, 176.4 kHz or 192 kHz. ...

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NXP Semiconductors In the above equation f The definition of the quality factor is the center frequency divided by the 3 dB bandwidth, see Equation ( 30 dB -----------------; f 2 Each band filter can be programmed to ...

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NXP Semiconductors The ranges of the TFA9812 parametric equalizer settings for each band are: • The Gain from +12 dB. • The center frequency, f • The quality factor Q is from ...

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NXP Semiconductors Equation example, in word2 bits [14:8] = [0111 010] represent k Table 15. Word word1 word1 word1 word2 word2 word2 ...

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NXP Semiconductors Gain (dB) Fig 7. Gain (dB) Fig 8. 8.5.2 Digital volume control control mode both audio channels have separate digital volume control. In Legacy control mode the volume control of both channels is common ...

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NXP Semiconductors Table 16. [7:0] control value (hexadecimal ... Section 9 In Legacy mode the pin AVOL (32) can be used to control the volume. Voltage levels of 0 2.8 V correspond linearly ...

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NXP Semiconductors Table 17. GAIN pin value The I C controls for selecting the +24 dB gain can be found in pin has no function In I The TFA9812 features also specific gain settings which are related ...

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NXP Semiconductors The selected PWM switching frequency is 400 kHz by default and can be set to 350 kHz, 700 kHz and 750 kHz in I this scales linearly if 32 kHz or 48 kHz is used as f Remark: ...

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NXP Semiconductors 8.7.1 Thermal foldback If the junction temperature of the TFA9812 exceeds the programmable Thermal foldback threshold temperature the gain of the amplifier is decreased gradually to a level where the combination of dissipation (P) and the thermal resistance ...

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NXP Semiconductors Table 20. Pin name V DDA V DDA(3V3) 8.7.6 Overdissipation protection When the output current of the power amplifiers exceeds a current value and the temperature is above 140 C, overdissipation protection is activated and ...

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NXP Semiconductors 8.7.11 Invalid BCK protection The BCK clock signal is verified as being at one of the allowed relative frequencies 3-state mode to prevent audible effects. The MCLK clock signal ...

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NXP Semiconductors Table 21. Protections Symbol Conditions OFP IBP [1] See, [2] Window Protection is only checked at power-up bus interface and register settings 2 9 bus interface The TFA9812 supports the 400 kHz ...

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NXP Semiconductors 2 9 write cycle description Table 25 byte size is 8 bits. The I written in pairs of two bytes. Data transfer is always MSB first. The cycle format for writing to the TFA9812 using SDA ...

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NXP Semiconductors 9. The TFA9812 sends the first byte. This is the most significant byte of the register. 10. The microcontroller asserts an acknowledge. 11. The TFA9812 sends the second byte. 12. The microcontroller asserts either an acknowledge or a ...

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NXP Semiconductors Table 27. Register address (hex) 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 Reserved ...

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NXP Semiconductors 9.5.1 Interpolator settings and soft mute Table 28. Register address 00h: miscellaneous I Bit 15 Symbol RSD RSD Default 0 Bit 7 Symbol RSD INV_POL Default 0 Table 29. Bit ...

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NXP Semiconductors Table 31. Bit 9.5.3 Digital input format Table 32. Register address 02h: digital input format Bit 15 Symbol RSD RSD Default 0 Bit 7 Symbol RSD RSD Default 0 Table 33. Bit ...

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NXP Semiconductors Table 35. Bit 1 0 9.5.5 Equalizer settings Table 36. Register addresses xxh = 04, 06...2A For word1 for equalizer 'yy' see Figure 9 Bit 15 Symbol Eyy_t Eyy_k 1 [1] Default - Bit 7 Symbol Eyy_k 3 ...

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NXP Semiconductors Left in Right in Fig 9. Equalizer configuration and register location mapping Table 38. Bit Table 39. Bit TFA9812_2 Preliminary ...

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NXP Semiconductors Table 40. Default configuration equalizer for f Band A1/B1 A2/B2 Frequency 31 63 (Hz) Q-factor 1 1 Gain (dB 9.5.6 PWM signal control Table 41. Register 2Ch: PWM signal control Bit 15 14 Symbol RSD RSD ...

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NXP Semiconductors 9.5.7 Digital-in clock configuration Table 43. Register 2Dh: digital-in clock configuration Bit 15 Symbol RSD RSD Default 0 Bit 7 Symbol RSD RSD Default 0 Table 44. Bit 9.5.8 Thermal foldback control Table 45. ...

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NXP Semiconductors Table 46. Bit 9.5.9 TFA9812 temperature Table 47. Register 2Fh: TFA9812 temperature Bit 15 Symbol RSD RSD Default - Bit 7 Symbol TEMP7 TEMP6 Default - Table 48. Bit 9.5.10 Miscellaneous status ...

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NXP Semiconductors Table 50. Bit [1] The diagnostic pin 30 DIAG is flagged when several protection mechanisms have been active, see Section 9.6 Overview of functional control in each control mode Table 51 functions described in ...

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NXP Semiconductors Table 51 fixed control setting, determined by default I supported (i.e. all options implemented in the TFA9812). Control function Clip level control Output power limit level control PWM signal frequency selection Thermal foldback threshold temperature control ...

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NXP Semiconductors Table 52. Pin 10/11 18/19 26/ TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Internal circuitry …continued Symbol Equivalent circuitry STABA STABD REFA V ...

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NXP Semiconductors Table 52. Pin 13/14 16/17 20/21 23/ TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Internal circuitry …continued Symbol Equivalent circuitry OUT2N OUT1P OUT2P OUT1N DIAG ...

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NXP Semiconductors Table 52. Pin 11. Limiting values Table 53. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V analog supply voltage DDA V power supply voltage DDP V ...

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NXP Semiconductors Table 53. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V voltage on pin electrostatic discharge voltage esd [ REFA = REFD ...

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NXP Semiconductors 13. Characteristics 13.1 DC Characteristics Table 55. DC characteristics Unless specified otherwise, V DDA REFD = REFA = SS1 SS2 MCLK clock mode, typical application diagram Symbol Parameter Supply voltage V ...

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NXP Semiconductors Table 55. DC characteristics …continued Unless specified otherwise, V DDA REFD = REFA = SS1 SS2 MCLK clock mode, typical application diagram Symbol Parameter V HIGH-level output OH voltage V LOW-level ...

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NXP Semiconductors Table 55. DC characteristics …continued Unless specified otherwise, V DDA REFD = REFA = SS1 SS2 MCLK clock mode, typical application diagram Symbol Parameter Thermal Foldback (TF) T thermal foldback act(th_fold) ...

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NXP Semiconductors 13.2 AC characteristics Table 56. AC characteristics Unless specified otherwise, V DDA kHz 44.1 kHz 400 kHz, 24-bit Symbol Parameter Output power per channel P RMS output ...

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NXP Semiconductors Table 56. AC characteristics …continued Unless specified otherwise, V DDA kHz 44.1 kHz 400 kHz, 24-bit Symbol Parameter t propagation delay PD PWM output t rise time ...

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NXP Semiconductors 2 Table 57. Characteristics I C bus interface; see 2 3 DDD(3V3) DDA(3V3) unless otherwise specified. Symbol Parameter t set-up time for STOP condition SU;STO t bus free time between ...

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NXP Semiconductors = Maximum duty factor (0.96). max The output power THD can be estimated using P (10%) O Figure 11 THD = function of BTL supply voltage for different load impedances. 30 ...

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NXP Semiconductors Remark: A 4.8 used supply voltage without running into current limiting. Current limiting (clipping) will avoid audio holes, but it causes a distortion comparable to voltage clipping. 14.3 Speaker configuration and impedance ...

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I S slave mode and Legacy control mode DIAGNOSTIC POWERUP DC-VOLUME CONTROL ENABLE ADSEL1/PLIM1 38 SCL/SFOR 39 SDA/ DDD(3V3) DDD 41 STABD C vddd C STABD 1 F 100 nF 42 REFD ...

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I S slave mode and I DIAGNOSTIC POWERUP ENABLE 3 ADSEL1/PLIM1 SCL 38 SCL/SFOR SDA SDA/MS 40 VDDD V DDD(3V3) 41 STABD C VDDD C STABD 100 ...

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I S master mode and Legacy control mode DIAGNOSTIC POWERUP DC-VOLUME CONTROL ENABLE ADSEL1/PLIM1 38 SCL/SFOR 39 3.3 V SDA/ DDD(3V3) DDD 41 STABD C vddd C STABD 1 F 100 nF ...

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I S master mode and I DIAGNOSTIC POWERUP ENABLE 3 ADSEL1/PLIM1 SCL 38 SCL/SFOR SDA SDA/MS 40 VDDD V DDD(3V3) 41 STABD C VDDD C STABD 100 ...

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NXP Semiconductors 14.5 Curves measured in typical application 10 THD+N (%) 1 ( kHz i ( kHz i ( 100 ...

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NXP Semiconductors 10 THD+N (%) Fig 18. Total harmonic distortion-plus-noise as a function of frequency 3 G ...

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NXP Semiconductors 0 SVRR (dB 100 500 mV (RMS) reference to ground; P ripple No input signal ( ( ...

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NXP Semiconductors (W/chan (1) Power limiter = 0 dB (2) Power limiter = 1.5 dB (3) Power limiter = 3 dB (4) Power limiter = 4 ...

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NXP Semiconductors 3 P ( kHz; Power dissipation in junction only ...

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NXP Semiconductors 15. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index ...

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NXP Semiconductors 16. Handling information It is advisable to abide by the normal precautions appropriate to handling MOS devices. TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Rev. 02 — 22 January 2009 TFA9812 2 S input ...

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NXP Semiconductors 17. Revision history Table 59. Revision history Document ID Release date TFA9812_2 20090122 • Modifications: Table 55 “DC characteristics” TFA9812_1 2008/10/30 TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Data sheet status Change notice Preliminary ...

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NXP Semiconductors 18. Legal information 18.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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NXP Semiconductors 18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19 Contact information ...

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