LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 123
LSI53C875
Manufacturer Part Number
LSI53C875
Description
PCI to Ultra SCSI I/O Processor
Manufacturer
LSI Logic
Datasheet
1.LSI53C875.pdf
(314 pages)
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DHP
CON
RST
AESP
Disable Halt on Parity Error or ATN (Target Only)
The DHP bit is only defined for target mode. When this
bit is cleared, the LSI53C875 halts the SCSI data transfer
when a parity error is detected or when the SATN/ signal
is asserted. If SATN/ or a parity error is received in the
middle of a data transfer, the LSI53C875 may transfer up
to three additional bytes before halting to synchronize
between internal core cells. During synchronous
operation, the LSI53C875 transfers data until there are
no outstanding synchronous offsets. If the LSI53C875 is
receiving data, any data residing in the DMA FIFO is sent
to memory before halting.
When this bit is set, the LSI53C875 does not halt the
SCSI transfer when SATN/ or a parity error is received.
Connected
This bit is automatically set any time the LSI53C875 is
connected to the SCSI bus as an initiator or as a target.
It is set after the LSI53C875 successfully completes
arbitration or when it has responded to a bus-initiated
selection or reselection. This bit is also set after the chip
wins simple arbitration when operating in low level mode.
When this bit is cleared, the LSI53C875 is not connected
to the SCSI bus.
The CPU can force a connected or disconnected
condition by setting or clearing this bit. This feature is
used primarily during loopback mode.
Assert SCSI RST/ Signal
Setting this bit asserts the SRST/ signal. The SRST/
output remains asserted until this bit is cleared. The
25 s minimum assertion time defined in the SCSI
specification must be timed out by the controlling
microprocessor or a SCRIPTS loop.
Assert Even SCSI Parity (force bad parity)
When this bit is set, the LSI53C875 asserts even parity.
It forces a SCSI parity error on each byte sent to the
SCSI bus from the chip. If parity checking is enabled,
then the LSI53C875 checks data received for odd parity.
This bit is used for diagnostic testing and should be
cleared for normal operation. It is useful to generate
parity errors to test error handling functions.
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