LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 63
LSI53C875
Manufacturer Part Number
LSI53C875
Description
PCI to Ultra SCSI I/O Processor
Manufacturer
LSI Logic
Datasheet
1.LSI53C875.pdf
(314 pages)
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2.6.2 Power State D3
Power state D3 is the minimum power state, which includes subsettings
called D3hot and D3cold. The devices are considered to be in power
state D3cold when power is removed from them. D3cold can transition
to D0 by applying V
and resetting the device. D3hot allows the device
CC
to transition to D0 using software. To obtain power reduction in D3hot,
the SCSI clock and the SCSI clock doubler Phase Lock Loop (PLL) are
disabled. Furthermore, the function’s soft reset is continually asserted
while in power state D3, which clears all pending interrupts and 3-states
the SCSI bus. In addition, the function’s PCI
Command
register is
cleared.
Power Management
2-39
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