LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 90
LSI53C875
Manufacturer Part Number
LSI53C875
Description
PCI to Ultra SCSI I/O Processor
Manufacturer
LSI Logic
Datasheet
1.LSI53C875.pdf
(314 pages)
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3-26
PMES
D2S
D1S
R
DSI
APS
PMEC
VER
Register: 0x44
Power Management Control/Status
Read/Write
This register applies to the LSI53C875E only and indicates the power
management control and status descriptions.
PCI Functional Description
PST DSCL
15
0
14 13 12
0
0
0
PME Support
This field is always set to 00000b because the
LSI53C875E does not provide a PME signal.
D2 Support
This device does not support the D2 power management
state, and this bit is set to zero.
D1 Support
This device does not support the D1 power management
state, and this bit is set to zero.
Reserved
Device Specific Initialization
This bit is set to 0 to indicate that the device requires no
special initialization before the generic class device driver
is able to use it.
Auxiliary Power Source
Because the device does not provide a PME signal, this
bit always returns a 0. This indicates that no auxiliary
power source is required to support the PME signal in the
D3cold power management state.
PME Clock
This bit always returns a zero value because the devices
do not provide a PME signal.
Version
This field is set to 001b to indicate that the device
complies with Revision 1.0 of the PCI Power
Management Interface Specification.
0
DSLT
0
9
0
PEN
8
0
7
0
0
0
R
0
0
2
0
1
0
[15:11]
PWS
[8:6]
[2:0]
0
0
10
9
5
4
3
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