CY7C1041CV33 Cypress Semiconductor, CY7C1041CV33 Datasheet - Page 4

• Manufacturer Part Number: CY7C1041CV33
• Description: 256K x 16 Static RAM
• Manufacturer: Cypress Semiconductor

AC Switching Characteristics
Document #: 38-05134 Rev. *D
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Shaded areas contain advance information.
Notes:
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
4.
5.
6.
7.
8.
9.
Parameter
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
t
t
At any given temperature and voltage condition, t
The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the Write.
The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
POWER
HZOE
[5]
, t
HZCE
gives the minimum amount of time that the power supply should be at typical V
[8, 9]
, and t
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low-Z
WE LOW to High-Z
Byte Enable to End of Write
CC
(typical) to the first access
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
Description
[7]
[6, 7]
[6, 7]
[7]
[6, 7]
[4]
Over the Operating Range
HZCE
is less than t
Min. Max. Min. Max.
1
8
3
0
3
0
0
8
6
6
0
0
6
4
0
3
6
-8
LZCE
8
8
4
4
4
8
4
6
4
, t
HZOE
10
10
1
3
0
3
0
0
7
7
0
0
7
5
0
3
7
is less than t
-10
10
10
10
5
5
5
5
6
5
CC
values until the first memory access can be performed.
LZOE
Min.
HZWE
12
12
1
3
0
3
0
0
8
8
0
0
8
6
0
3
8
, and t
-12
and t
Max.
HZWE
12
12
12
SD
6
6
6
6
6
6
.
is less than t
Min.
15
15
10
10
10
10
1
3
0
3
0
0
0
0
7
0
3
-15
Max.
LZWE
15
15
15
7
7
7
7
7
7
CY7C1041CV33
for any given device.
Min.
20
20
10
10
10
10
1
3
0
3
0
0
0
0
8
0
3
-20
Max.
Page 4 of 11
20
20
20
8
8
8
8
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s