PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 106

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
Third Command Phase Byte
Bit 0 - DMA
Bits 3-0 - Delay Before Processing Factor
Data Transfer
Data Transfer
Data Transfer
Rate (bps)
Rate (bps)
This bit selects the data transfer mode in the execution
phase of a read, write, or scan operation.
Data can be transferred between the microprocessor
and the controller during execution in DMA mode or in
non-DMA mode, i.e., interrupt transfer mode or software
polling mode.
See “Execution Phase” on page 78 for a description of
these modes.
0 - DMA mode is selected.
1 - Non-DMA mode is selected.
These bits specify a factor that is multiplied by a con-
stant to determine the delay before command process-
ing starts, i.e., from selection of a drive motor until a
read or write operation starts.
The value of the Motor Timer Values (TMR) bit (bit 7) of
the second command phase byte in the MODE com-
mand determines which group of constants and delay
ranges to use. See “Bit 7 - Motor Timer Values (TMR)”
on page 93.
Rate (bps)
TABLE 5-26. STEP Time Interval Calculation
500 K
300 K
250 K
500 K
300 K
250 K
500 K
300 K
250 K
1 M
1 M
1 M
TABLE 5-25. Constant Multipliers for Delay Before Processing Factor and Delay Ranges
TABLE 5-24. Constant Multipliers for Delay After Processing Factor and Delay Ranges
Calculation of Time
Constant Multiplier
Constant Multiplier
(16
(16
(16
(16
Interval
SRT) x 1.67
80 / 3
10 / 3
SRT) x 2
SRT) / 2
16
32
8
1
1
4
SRT)
Bit 7 of MODE (TMR) = 0
Bit 7 of MODE (TMR) = 0
Range (msec)
Permitted Range (msec)
Permitted Range (msec)
1.67 - 26.7
Permitted
0.5 - 8
1 - 16
2 - 32
26.7 - 427
3.3 - 427
16 - 256
32 - 512
4 - 512
8 -128
1 -128
1 -128
106
Execution Phase
Internal registers are written.
Result Phase
None.
5.7.22 The VERIFY Command
The VERIFY command verifies the contents of data and/or
address fields after they have been formatted or written.
VERIFY reads logical sectors containing a normal data Ad-
dress Mark (AM) from the selected drive, without transfer-
ring the data to the host.
The TC signal cannot terminate this command since no
data is transferred. Instead, VERIFY simulates a TC signal
by setting the Enable Count (EC) bit to1. In this case, VER-
IFY terminates when the number of sectors read equals the
number of sectors to read, i.e., Sectors to read Count (SC).
If SC = 0 then 256 sectors will be verified.
When EC is 0, VERIFY ends when the End of the Track
(EOT) sector number equals the number of the sector
checked. In this case, the ninth command phase byte is not
needed and should be set to FFh.
Table 5-27 shows how different values for the VERIFY pa-
rameters affect termination.
The specific constant that will be multiplied by this factor
to determine the actual delay before processing for
each data transfer rate is shown in Table 5-25.
Use the smallest possible value for this factor, except 0,
i.e., 1. If this factor is 0, the value128 is used.
Constant Multiplier
Constant Multiplier
2560 / 3
160 / 3
1024
512
512
32
32
64
Bit 7 of MODE (TMR) = 1
Bit 7 of MODE (TMR) = 1
Permitted Range (msec)
Permitted Range (msec)
1024 -16384
853 - 13653
512 - 8192
512 - 8192
32 - 4096
32 - 4096
53 - 6827
64 - 8192