PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 119

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

EPP 1.9 Data Write and (Backward) Data Read
This procedure writes to the selected peripheral drive or
register.
EPP 1.9 data read and write operations are similar to EPP
1.9 address read and write operations, except that the data
strobe (DSTRB signal) and EPP Data register replace the
address strobe (ASTRB signal) and the EPP Address reg-
ister, respectively.
6.4 EXTENDED CAPABILITIES PARALLEL PORT
In the Extended Capabilities Port (ECP) modes, the device
is a state machine that supports a 16-byte FIFO that can be
configured for either direction, command and data FIFO
tags (one per byte), a FIFO threshold interrupt for both di-
rections, FIFO empty and full status bits, automatic genera-
tion of strobes (by hardware) to fill or empty the FIFO,
transfer of commands and data, and Run Length Encoding
(RLE) expanding (decompression) as explained below. The
FIFO can be accessed by PIO or system DMA cycles.
6.4.1
ECP modes are enabled at as described in Table 6-1 on
page 112. The ECP mode is selected at reset by setting bits
7-5 of the SuperI/O Parallel Port Configuration register at in-
dex F0h (see Section 2.7.1 on page 37) to 100 or 111.
Thereafter, the mode is controlled via the bits 7-5 of the
ECP Extended Control Register (ECR) at offset 402h of the
parallel port. See Section 6.5.12 on page 124.
Table 6-9 lists the ECP modes. See Table 6-11 on page 129
and Section 6.6 on page 128 for more detailed descriptions
of these modes.
6.4.2
Software should operate as described in “ Extended Capa-
bilities Port Protocol and ISA Interface Standard” .
Some of these operations are:
•
IOCHRDY
Software should enable ECP after bits 3-0 of the parallel
port Control Register (CTR) are set to 0100.
ASTRB
WRITE
(ECP)
PD7-0
WAIT
D7-0
ZWS
ECP Modes
Software Operation
RD
FIGURE 6-16. EPP 1.9 Address Read
Parallel Port (Logical Device 4)
119
5. Software should switch to mode 100 when bits 0, 1 and
6. Software should switch from mode 100 to mode 000 or
7. When the ECP is in mode 100, software should write 0
Software may switch from mode 011 backward to modes
000 or 001, when there is an on-going ECP read cycle. In
this case, the read cycle is aborted by deasserting AFD.
The FIFO is reset (empty) and a potential byte expansion
(RLE) is automatically terminated since the new mode is
000 or 001.
6.4.3
The ZWS signal is asserted by the ECP when ECP modes
are enabled, and an ECP register is accessed by system
PIO instructions, thus using a system zero wait states cycle
(except during read cycles from ECR).
The ECP uses an internal clock, which can be frozen to re-
duce power consumption during power down. In this power-
down state the DMA is disabled, all interrupts (except ACK)
are masked, and the FIFO registers are not accessible (ac-
cess is ignored). The other ECP registers are unaffected by
power-down and are always accessible when the ECP is
enabled. During power-down the FIFO status and contents
become inaccessible, and the system reads bit 2 of ECR as
0, bit 1 of ECR as 1 and bit 0 of ECR as 1, regardless of the
actual values of these bits. The FIFO status and contents
are not lost, however, and when the clock activity resumes,
the values of these bits resume their designated functions.
When the clock is frozen, an on-going ECP cycle may be
corrupted, but the next ECP cycle will not start even if the
FIFO is not empty in the forward direction, or not full in the
backward direction. If the ECP clock starts or stops toggling
during a system cycle that accesses the FIFO, the cycle
may yield wrong data.
ECP output signals are inactive when the ECP is disabled.
Only the FIFO, DMA and RLE do not function when the
clock is frozen. All other registers are accessible and func-
tional. The FIFO, DMA and RLE are affected by ECR mod-
ifications, i.e., they are reset when exits from modes 010 or
011 are carried out even while the clock is frozen.
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•
•
•
•
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When ECP is enabled, software should switch modes
only through modes 000 or 001.
When ECP is enabled, the software should change di-
rection only in mode 001.
Software should not switch from mode 010 or 011, to
mode 000 or 001, unless the FIFO is empty.
Software should switch to mode 011 when bits 0 and 1
of DCR are 0.
Software should switch to mode 010 when bit 0 of DCR
is 0.
Software should disable ECP only in mode 000 or 001.
3 of the DCR are 0.
001 only when bit 7 of the DSR (BUSY) is 1. Otherwise,
an on-going EPP cycle can be aborted.
to bit 5 of the DCR before performing EPP cycles.
Hardware Operation
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