PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 24

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
2.0 Configuration
The part is partially configured by hardware, during reset.
The configuration can also be changed by software, by
changing the values of the configuration registers.
The configuration registers are accessed using an Index
register and a Data register. During reset, hardware strap-
ping options define the addresses of the configuration reg-
isters. See Section 2.1.2.
After the Index and Data register pair have determined the
addresses of the configuration registers, the addresses of
the Index and Data registers can be changed within the ISA
I/O address space, and a 16-bit programmable register con-
trols references to their addresses and to the addresses of
the other registers.
This chapter describes the hardware and software configu-
ration processes. For each, it describes configuration of the
Index and Data register pair first. See Sections 2.1 and 2.2.
Section 2.3 starting on page 26 presents an overview of the
configuration registers of the part and describes each in de-
tail.
2.1 HARDWARE CONFIGURATION
The part supports two Plug and Play (PnP) configuration
modes that determine the status of register addresses upon
wake up from a hardware reset, Full PnP ISA mode and
PnP Motherboard mode.
2.1.1
During reset, strapping options on the BADDR0 and
BADDR1 pins determine one of the following modes.
•
•
BADDR1
Full Plug and Play ISA mode – System wakes up in
Wait for Key state.
Index and Data register addresses are as defined by Mi-
crosoft and Intel in the “Plug and Play ISA Specification,
Version 1.0a, May 5, 1994.”
Plug and Play Motherboard mode – system wakes up
in Config state.
The BIOS configures the part. Index and Data register
addresses are different from the addresses of the PnP
Index and Data registers. Configuration registers can be
accessed as if the serial isolation procedure had already
been done, and the part is selected.
0
1
1
Wake Up Options
BADDR0
0
1
x
015Ch Read/Write
002Eh Read/Write
Index Register
Write Only
0279h
TABLE 2-1. Base Addresses
Address
Configuration
Read: RD_DATA Port
24
015Dh Read/Write
002Fh Read/Write
Data Register
2.1.2
During reset, a hardware strapping option on the BADDR0
and BADDR1 pins defines an address for the Index and
Data Register pair. This prevents contention between the
registers for I/O address space.
Table 2-1 shows the base addresses for the Index and Data
registers that hardware sets for each combination of values
of the Base Address strap pins (BADDR0 and BADDR1).
You can access and change the content of the configuration
registers at any time, as long as the base addresses of the
Index and Data registers are defined.
When BADDR1 is low (0), the PnP protocol defines the ad-
dresses of the Index and Data register, and the system
wakes up from reset in the Wait for Key state.
When BADDR1 is high (1), the addresses of the Index and
Data register are according to Table 2-1, and the system
wakes up from reset in the Config state.
This configures the part with default values, automatically,
without software intervention. After reset, use software as
described in Section 2.2 to modify the selected base ad-
dress of the Index and Data register pair, and the defaults
for configuration registers.
The Plug and Play soft reset has no effect on the logical de-
vices, except for the effect of the Activate registers (index
30h) in each logical device.
The part can wake up with the FDC, the KBC and the RTC
either active (enabled) or inactive (disabled). The clock mul-
tiplier, if configured via CFG3,2 strap pins, wakes up en-
abled. The other logical devices wake up inactive
(disabled).
Write: 0A79h
The BIOS may switch the addresses of the Index and
Data registers to the PnP ISA addresses of the Index
and Data registers, by using software to modify the base
address bits of the SuperI/O Configuration 2 register (at
Index 22h). See Section 2.4.4
The Index and Data Register Pair
Wake up in Wait for Key state
Wake up in Config state
Wake up in Config state
PnP Motherboard Mode
PnP Motherboard Mode
Configuration Type
Full PnP ISA Mode