PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 76

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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Bit 5 - Undefined
Bit 6 - Low Power
Bit 7 - Software Reset
Track 0 is the default starting track number for precom-
pensation. The starting track number can be changed
using the CONFIGURE command.
Should be set to 0.
This bit triggers a manual power down of the FDC in
which the clock and data separator circuits are turned
off. A manual power down can also be triggered by the
MODE command.
After a manual power down, the FDC returns to normal
power after a software reset, or an access to the Data
Register (FIFO) or the Main Status Register (MSR).
0 - Normal power.
1 - Trigger power down.
This bit controls the same kind of software reset of the
FDC as bit 2 of the Digital Output Register (DOR). The
difference is that this bit is automatically cleared to 0 (no
reset) 100 nsec after it was set to 1.
See also “Bit 2 - Reset Controller” on page 72.
0 - No reset. (Default)
1 - Reset.
TABLE 5-8. Default Precompensation Delays
TABLE 5-7. Write Precompensation Delays
Data Rate
500 Kbps
300 Kbps
250 Kbps
4
0
0
0
0
1
1
1
1
1 Mbps
DSR Bits
3
0
0
1
1
0
0
1
1
2
0
1
0
1
0
1
0
1
Duration of Delay
Default (Table 5-8)
Precompensation Delay
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
125.0 nsec
166.7 nsec
208.3 nsec
250.0 nsec
41.7 nsec
83.3 nsec
0.0 nsec
125.0 nsec
125.0 nsec
125.0 nsec
41.7 nsec
76
5.3.7
The Data Register of the FDC is a read/write register that is
used to transfer all commands, data and status information
between the microprocessor and the FDC.
During the command phase, the microprocessor writes
command bytes into the Data Register after polling the
RQM (bit 7) and DIO (bit 6) bits in the MSR. During the re-
sult phase, the microprocessor reads result bytes from the
Data Register after polling the RQM and DIO bits in the
MSR.
Use of the FIFO buffer lengthens the interrupt latency peri-
od and, thereby, reduces the chance of a disk overrun or
underrun error occurring. Typically, the FIFO buffer is used
at a 1 Mbps data transfer rate or with multi-tasking operating
systems.
Enabling and Disabling the FIFO Buffer
The 16-byte FIFO buffer can be used for DMA, interrupt, or
software polling type transfers during the execution of a
read, write, format or scan command.
The FIFO buffer is enabled and its threshold is set by the
CONFIGURE command.
When the FIFO buffer is enabled, only execution phase byte
transfers use it. If the FIFO buffer is enabled, it is not dis-
abled after a software reset if the LOCK bit is set in the
LOCK command.
The FIFO buffer is always disabled during the command
and result phases of a controller operation. A hardware re-
set disables the FIFO buffer and sets its threshold to zero.
The MODE command can also disable the FIFO for read or
write operations separately.
After a hardware reset, the FIFO buffer is disabled to main-
tain compatibility with PC-AT systems.
Burst Mode Enabled and Disabled
The FIFO buffer can be used with burst mode enabled or
disabled by the MODE command.
In burst mode, the DRQ or IRQ signal assigned to the FDC
remains active until all of the bytes have been transferred to
or from the FIFO buffer.
When burst mode is disabled, the appropriate DRQ or IRQ
signal is deactivated for 350 nsec to allow higher priority
transfer requests to be processed.
FIFO Buffer Response Time
During the execution phase of a command involving data
transfer to or from the FIFO buffer, the maximum time the
system has to respond to a data transfer service request is
calculated by the following formula:
This formula applies for all data transfer rates, whether the
FIFO buffer is enabled or disabled. THRESH is a 4-bit value
programmed by the CONFIGURE command, which sets
the threshold of the FIFO buffer. If the FIFO buffer is dis-
abled, THRESH is zero in the above formula. The last term
in the formula, (16 x t
crocode overhead required by the FDC. This delay is also
data rate dependent. Table 13-36 on page 192 specifies
minimum and maximum values for t
Max_Time = (THRESH + 1) x 8 x t
Data Register (FIFO), Offset 05h
ICP
) is an inherent delay due to the mi-
DRP
DRP
and t
– (16 x t
ICP
.
ICP
)