AD775 Analog Devices, AD775 Datasheet
AD775
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AD775 Summary of contents
Page 1
... The low input capacitance (11 pF typical) provides an easy-to-drive input load compared to conventional flash converters. The AD775 is offered in both 300 mil SOIC and 400 mil DIP plastic packages, and is designed to operate over an extended commercial temperature range (– +75 C). ...
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... NSTC 40 IRE modulation ramp, CLOCK = 14.3 MSPS amplitude = 0.3 dB full scale. IN Specifications subject to change without notice. See Definition of Specifications for additional information +25 C with CLOCK = 20 MHz unless otherwise noted) AD775J Min Typ 8 +0.5 0.3 GUARANTEED –10 –35 0 +15 1.0 0.5 2 – ...
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... 5.25 OZ Min SAMPLE N+2 SAMPLE N+1 SAMPLE DATA N-3 DATA N-2 Figure 1. AD775 Timing Diagram –3– 2 +0 AD775J Min Typ Max 4.0 1.0 5 –5 5 –1.1 16 3.7 16 Typ Max Units 35 MHz ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Model Range AD775JN – +75 C 24-Pin 400 Mil Plastic DIP N-24B AD775JR – +75 C 24-Pin 300 Mil SOIC –4– ...
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... Figure 6. Typical FFT at 5 MHz Input, 20 MSPS Clock Rate (V = –0.5 dB –1 +FULLSCALE –FULLSCALE Figure 7. Typical Integral Nonlinearity (INL) –5– AD775 0 – MHz 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 FREQUENCY – MHz 10 9.0 10.0 +FULLSCALE ...
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... The analog input range is determined by the voltages applied to the bottom and top of the ladder, and the AD775 can digitize inputs down using a single sup- ply. On-chip application resistors are provided to allow the ladder to be conveniently biased by the supply voltage. ...
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... In order to level shift the ground-based input signal to the dc level required by the input of the AD775, the supply voltage is resis- tively divided to produce the appropriate voltage at the nonin- verting input of the AD817. For most applications, the AD817 provides a low cost, high performance level shifter ...
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... MSPS, a 50% duty cycle clock is recommended. For slower sampling applications, the AD775 can accommodate a wider range of duty cycles, provided each clock phase is as least 25 ns. Under certain conditions, the AD775 can be operated at sam- pling rates above 20 MSPS. Figure 14 shows the signal-to-noise plus distortion (S/(N+D)) performance of a typical AD775 versus clock frequency ...
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... Q1, an emitter-follower, buffers the input signal and provides ample current to drive a simple low-pass filter. The filtering is included to limit wideband noise and highlight the fact that the AD775 can be driven from a nonzero source impedance. The reference circuit is similar to the one shown in Figure 11 ...
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... An additional inverter is used to provide a buffered clock signal whose rising edges indicate that data is valid. A 74ALS541 buffers the eight digital data outputs of the AD775 to improve the load driving capability. The multilayer PCB board layout shows some of the important design guidelines recommended for the AD775 ...
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... Figure 18. Silkscreen Layer (Not to Scale) Figure 19. Component Side PCB Layout (Not to Scale) REV. 0 Figure 20. Solder Side PCB Layout (Not to Scale) Figure 21. Ground Plane PCB Layout (Not to Scale) –11– AD775 ...
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... AD775 Figure 22. Power Plane PCB Layout (Not to Scale) Plastic DIP (N-24B 0.346 (8.80) PIN 1 0.330 (8.40 1.205 (30.60) 0.020 1.185 (30.10) (0.50) MIN 0.200 (5.05) 0.125 (3.18) 0.118 (3.00) MIN 0.024 (0.60) 0.053 (1.35) SEATING 0.100 (2.54) PLANE 0.016 (0.40) 0.041 (1.05) BSC OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24 PIN 1 1 0.400 (10.16) ...