IDT71216S12PF Integrated Device Technology, IDT71216S12PF Datasheet

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IDT71216S12PF

Manufacturer Part Number
IDT71216S12PF
Description
BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For PowerPCO and RISC Processors
Manufacturer
Integrated Device Technology
Datasheet
FEATURES:
• 16K x 15 Configuration
• Match output uses Valid bit to qualify MATCH output
• High-Speed Address-to-Match comparison times
• Asynchronous Read/Match operation with Synchronous
• Separate
• Separate
• Synchronous
• Dual Chip selects for easy depth expansion with no
• I/O pins both 5V TTL and 3.3V LVTTL compatible with
• Packaged in a 80-pin Thin Plastic Quad Flat Pack
DESCRIPTION:
organized 16K x 15 and designed to support PowerPC and
other RISC processors at bus speeds up to 66MHz. There are
twelve common I/O TAG bits, with the remaining three bits
used as status bits. A 12-bit comparator is on-chip to allow fast
comparison of the twelve stored TAG bits and the current Tag
input data. An active HIGH MATCH output is generated when
these two groups of data are the same for a given address.
PIN DESCRIPTIONS
COMMERCIAL TEMPERATURE RANGE
The IDT logo is a registered trademark and CacheRAM is a trademark of Integrated Device Technology, Inc.
PowerPC is a trademark of International Business Machines, Inc.
1996 Integrated Device Technology, Inc.
– 12 TAG Bits
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
– 8/9/10/12ns over commercial temperature range
TA
speed operation
Write and Reset operation
performance degredation
V
PWRDN
(TQFP)
Integrated Device Technology, Inc.
The IDT71216 is a 245,760-bit Cache Tag StaticRAM,
A
CS1
WET
WES
OET
OES
RESET
PWRDN
SFUNC
TT1
VLD
DTY
WT
CCQ
0
circuitry included inside the Cache-Tag for highest
– A
IN
, CS2
IN
IN
pins
/ S
/ S
13
/ S
pin to place device in low-power mode
3IN
1IN
2IN
WE
OE
for the TAG bits, the Status bits, and
for the TAG bits and the Status bits
RESET
Address Inputs
Chip Selects
Write Enable - Tag Bits
Write Enable - Status Bits
Output Enable - Tag Bits
Output Enable - Status Bits
Status Bit Reset
Powerdown Mode Control Pin
Status Bit Function Control Pin
Read/Write Input from Processor
Valid Bit / S
Dirty Bit / S
Write Through Bit / S
pin for invalidation of all Tag entries
2
1
Bit Input
Bit Input
3
Bit Input
BiCMOS StaticRAM
240K (16K x 15-BIT)
CACHE-TAG RAM
For PowerPC and RISC Processors
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
TA
14.3
This high-speed MATCH signal, with t
provides the fastest possible enabling of secondary cache
accesses.
be configured for either dedicated or generic functionality,
depending on the SFUNC input pin. With SFUNC LOW, the
status bits are defined and used internally by the device,
allowing easier determination of the validity and use of the
given Tag data. SFUNC HIGH releases the defined internal
status bit usage and control, allowing the user to configure the
status bit information to fit his system needs. A synchronous
RESET
all status bits in the array for easy invalidation of all Tag
addresses.
knowledge (
upon MATCH, VLD bit, WT bit, and external inputs provided
by the user. This can significantly simplify cache controller
logic and minimize cache decision time. Match and Read
operations are both asynchronous in order to provide the
fastest access times possible, while Write operations are
synchronous for ease of system timing.
separate V
ance with both 5.0V TTL and 3.3V LVTTL Logic levels. The
PWRDN
power consumption by 90%, providing significant system
power savings.
high-reliability BiCMOS technology and is offered in a space-
saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.
The three separate I/O status bits (VLD, DTY, and WT) can
The IDT71216 also provides the option for Transfer Ac-
The IDT71216 uses a 5V power supply on Vcc, with
The IDT71216 is fabricated using IDT's high-performance,
CLK
TAH
TAOE
TAIN
TA
TAG
VLD
DTY
WT
MATCH
V
V
V
CC
CCQ
SS
OUT
OUT
pin, when held LOW at a rising clock edge, will reset
OUT
0
– TAG
pin offers a low-power standby mode to reduce
/ S
/ S
/ S
CCQ
TA
3OUT
1OUT
2OUT
) generation within the cache tag itself, based
11
pins provided for the outputs to offer compli-
System Clock
TA
TA
Additional
Transfer Acknowledge
Tag Data Input/Outputs
Valid Bit / S
Dirty Bit / S
Write Through Bit / S
Match
+5V Power
Output Buffer Power
Ground
Force High
Output Enable
TA
2
1
Bit Output
Bit Output
Input
3
Bit Output
ADM
as fast as 8ns,
AUGUST 1996
IDT71216
Output
Output
Output
Output
Output
QPwr
Input
Input
Input
Input
DSC-3067/3
Gnd
Pwr
1
3067 tbl 01
I/O

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IDT71216S12PF Summary of contents

Page 1

... Write Through Bit / S IN 3IN The IDT logo is a registered trademark and CacheRAM is a trademark of Integrated Device Technology, Inc. PowerPC is a trademark of International Business Machines, Inc. COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM ...

Page 2

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM PIN CONFIGURATION DTY / ...

Page 3

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM FUNCTIONAL BLOCK DIAGRAM ADDR (0:13) Reg CS1 CS2 Reg TAG (0:11) OET WRITE (pos) PULSE GENERATOR WET Reg WES CLK RESET (neg) PULSE GENERATOR RESET PWRDN SFUNC TT1 TAH TAIN Reg TAOE 0 ...

Page 4

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM TRUTH TABLES CHIP SELECT, RESET, AND POWER-DOWN FUNCTIONS CS1 RESET RESET PWRDN WET WES WET CS1 PWRDN CS2 CLK CHIP SELECT FUNCTION ...

Page 5

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM TRUTH TABLES (CONT.) ( MATCH FUNCTION CS1 CS1 OET WET OET WET WES WES CS2 SFUNC ...

Page 6

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. V Supply Voltage 4. Output Buffers 4.75 CCQ V 3.3V Output Buffers 3.0 CCQ V Supply Ground Input High Voltage ...

Page 7

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM AC ELECTRICAL CHARACTERISTICS (V = 5. CCQ Symbol Parameter Read Cycle t Address Access Time Tag Bits AAT t Chip Select Access Time Tag Bits ACST (1) ...

Page 8

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM AC ELECTRICAL CHARACTERISTICS (V = 5. CCQ Symbol Parameter Write Cycle and Clock Parameters t Clock Cycle Time CYC ( Clock Pulse HIGH CH (2, ...

Page 9

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM AC ELECTRICAL CHARACTERISTICS (V = 5. CCQ Symbol Parameter TA TA MATCH and Cycles t Address to MATCH Valid ADM t Data Input to MATCH Valid DAM ...

Page 10

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC Test Load AC TEST LOADS V CCQ Outputs 347 Figure 1. AC Test Load Tag ...

Page 11

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM TIMING WAVEFORMS OF WRITE AND READ CYCLES COMMERCIAL TEMPERATURE RANGE 14.3 11 ...

Page 12

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM TIMING WAVEFORMS OF MATCH AND TA TA FUNCTIONS 14.3 COMMERCIAL TEMPERATURE RANGE 12 ...

Page 13

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM RESET RESET TIMING WAVEFORMS OF CLK t SR RESET t PDSR PWRDN VLD OUT DTY OUT WT OUT t S WES WET TA MATCH TAG (0:11) NOTE: 1. Transition is measured 200mV from ...

Page 14

IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM OES OES TIMING WAVEFORMS OF OES VLD OUT DTY OUT Valid Output WT OUT NOTE: 1. Transition is measured 200mV from steady state. TIMING WAVEFORMS OF POWER DOWN FUNCTION PWRDN t WHPL CLK ...

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