CDP68HC68A2M Intersil Corporation, CDP68HC68A2M Datasheet
CDP68HC68A2M
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CDP68HC68A2M Summary of contents
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... Evaluation Board available - CDP68HC05C16BEVAL Ordering Information TEMP. RANGE o PART NUMBER ( C) CDP68HC68A2E - CDP68HC68A2M - CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | http://www.intersil.com or 407-727-9207 Copyright CDP68HC68A2 CMOS Serial 10-Bit A/D Converter Description The CDP68HC68A2 is a CMOS 8-bit or 10-bit successive ...
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... ACC LATCH COMPARATOR 3 MOSI 8 CONTROL REGISTER 4 DATA REGISTERS (READ ONLY) 4 CAR CHOPPER STABILIZED COMPARATOR SUCCESSIVE APPROXIMATION 10-BIT CAPACITOR ARRAY CAPACITOR SWITCH ARRAY AI0 CDP68HC68A2M (SOIC) TOP VIEW OSC INT 2 19 AI1 MISO 3 18 AI2 MOSI 4 17 AI3 NC 5 ...
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Absolute Maximum Ratings DC Supply Voltage Range -0.5V to +7V DD (Voltage Referenced to V Terminal) SS Input Voltage Range, All Inputs ...
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Electrical Specification PARAMETER DIGITAL OUTPUTS: MISO, INT -40 A High Level Output V , MISO OH Low Level Output V , MISO, INT OL Three-State Output Leakage I , MISO, INT ...
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Through this specification the CDP68HC68A2 is referred to simply as the A2. Functional Pin Description OSC - Oscillator (Input/Output) This pin is user programmable. In the “external” mode, the clock input for the successive approximation logic is applied to OSC ...
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HIGH DATA REGISTER 0 LOW DATA REGISTER 0 $01 HIGH DATA REGISTER 7 $0E LOW DATA REGISTER 7 $0F DATA REGISTERS $10 MODE SELECT REGISTER $11 CHANNEL SELECT REGISTER $12 START ADDRESS REGISTER $13 STATUS REGISTER CONTROL/STATUS REGISTERS FIGURE ...
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Software Interface Reading and writing to the A2 can be performed in either single byte or multiple byte (burst) modes. Both modes begin the same way: a positive transition is applied high, it must first ...
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Mode Select Register (MSR) Address/Control: (R/W)0010000 - $10 Read/Write: Yes EXT The read/write register is used to select the various modes of operation of the A2. Bits 6 and ...
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CSR. After the specified channel is converted, subsequent conversions proceed in ascending order, skipping channels not selected in the CSR. Therefore, jamming the CAR with a non-selected channel number ...
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B2, CA1 Channel Address, bit 1. See discussion under CA2. B1, CA0 Channel Address, bit 0. See discussion under CA2. Data Registers Address/Control: 0000000 to 0000111 - $00 to $0F Read/Write: Read Only High DV DOV 0 0 H/L = ...
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When all channels have been converted the INT and ACC flags in the SR are set, the INT pin is driven low ( true in the MSR), the CIP flag is cleared, and, if active, the internal oscillator ...
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SIGNAL INPUT D2 FIGURE 5A. ANALOG INPUT DURING SAMPLE TIME SIGNAL INPUT D2 FIGURE 5B. ANALOG INPUT DURING HOLD AND IDLE TIME The time constant ( ) for the input network is ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...