TC7117 TelCom, TC7117 Datasheet - Page 10

• Manufacturer Part Number: TC7117
• Description: 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
• Manufacturer: TelCom

TC7116
TC7116A
TC7117
TC7117A
3-212
System Timing
and TC7117/TC7117A is shown in Figure 9. Three clocking
methods may be used:
decade counters. It is then further divided to form the three
convert-cycle phases: signal integrate (1000 counts), refer-
ence deintegrate (0 to 2000 counts), and auto-zero (1000 to
3000 counts). For signals less than full scale, auto-zero gets
the unused portion of reference deintegrate. This makes a
complete measure cycle of 4000 (16,000 clock pulses)
independent of input voltage. For 3 readings per second, an
oscillator frequency of 48 kHz would be used.
OSC 1
The clocking method used for the TC7116/TC7116A
(1) An external oscillator connected to pin 40.
(2) A crystal between pins 39 and 40.
(3) An RC network using all three pins.
The oscillator frequency is
TYPICAL SEGMENT OUTPUT
40
DIGITAL GROUND
V +
FROM COMPARATOR OUTPUT
0.5 mA
8 mA
OSC
CLOCK
TC7117A
TC7117
39
2
TO SWITCH DRIVERS
SEGMENT
TO
V
+
OSC 3
4 before it clocks the
38
Figure 9. TC7117/TC7117A Digital Section
THOUSANDS
÷
4
7-SEGMENT
HUNDREDS
CONTROL LOGIC
DECODE
signal-integrate cycle should be a multiple of 60 Hz. Oscil-
lator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz, 48
kHz, 40 kHz, etc. should be selected. For 50 Hz rejection,
oscillator frequencies of 200 kHz, 100 kHz, 66-2/3 kHz, 50
kHz, 40 kHz, etc. would be suitable. Note that 40 kHz (2.5
readings per second) will reject both 50 Hz and 60 Hz.
HOLD Reading Input
updated. Analog-to-digital conversions will continue but will
not be updated until HLDR is returned to LOW. To continu-
ously update the display, connect to test (TC7116/TC7116A)
or ground (TC7117/TC7117A), or disconnect. This input is
CMOS compatible with 70 k
(TC7116/TC7116A) or ground (TC7117/TC7117A).
To achieve maximum rejection of 60-Hz pickup, the
When HLDR is at a logic HIGH the latch will not be
HLDR
1
3-1/2 DIGIT ANALOG-TO-DIGITAL
7-SEGMENT
LATCH
DECODE
TENS
~70 k
CONVERTERS WITH HOLD
TELCOM SEMICONDUCTOR, INC.
7-SEGMENT
DECODE
UNITS
typical resistance to TEST
500
35
37
21
DIGITAL
GND
V
TEST
+