CS5158 Cherry Semiconductor Corporation, CS5158 Datasheet - Page 6

• Manufacturer Part Number: CS5158
• Description: CPU 5-Bit Synchronous Buck Controller
• Manufacturer: Cherry Semiconductor Corporation

V
The V
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
Figure 1: V
The V
put voltage is used to generate both the error signal and the
ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V
advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this ‘slow’ feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote sens-
ing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compen-
sate for a deviation in either line or load voltage. This
2
TM
COMP
Control Method
2
2
TM
TM
2
method of control uses a ramp signal that is gen-
control method is illustrated in Figure 1. The out-
TM
Control Diagram
Theory of Operation
Signal
+
–
Error
Ramp
Signal
PWM
Comparator
C
Amplifier
2
Error
TM
control scheme has the same
V
V
GATE(H)
V
GATE(L)
FFB
E
+
–
V
Reference
Output
Voltage
FB
Voltage
Feedback
Applications Information
2
TM
6
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains fixed error signal under
deviation in the line voltage, since the slope of the ramp
signal changes, but still relies on a change in the error sig-
nal for a deviation in load. The V
maintains a fixed error signal for both line and load varia-
tion, since the ramp signal is affected by both line and load.
Constant Off Time
To maximize transient response, the CS5158 uses a constant
off time method to control the rate of output pulses. During
normal operation, the off time of the high side switch is ter-
minated after a fixed period, set by the C
maintain regulation, the V
time. The PWM comparator monitors the output voltage
ramp, and terminates the switch on time.
Constant off time provides a number of advantages. Switch
duty cycle can be adjusted from 0 to 100% on a pulse by
pulse basis when responding to transient conditions. Both
0% and 100% duty cycle operation can be maintained for
extended periods of time in response to load or line tran-
sients. PWM slope compensation to avoid sub-harmonic
oscillations at high duty cycles is avoided.
Switch on time is limited by an internal 30µs timer, mini-
mizing stress to the power components.
Programmable Output
The CS5158 is designed to provide two methods for pro-
gramming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.
The first range is 2.10V to 3.50V in 100mV steps, the second
is 1.30V to 2.05V in 50mV steps, depending on the digital
input code. If all five bits are left open, the CS5158 enters
adjust mode. In adjust mode, the designer can choose any
output voltage by using resistor divider feedback to the
V
Start Up
Until the voltage on the V
monitor threshold, the soft start and gate pins are held low.
The FAULT latch is reset (no Fault condition). The output
of the error amplifier (COMP) is pulled up to 1V by the
comparator clamp. When the V
threshold, the GateH output is activated, and the soft start
capacitor begins charging. The GateH output will remain
on, enabling the NFET switch, until terminated by either
the PWM comparator, or the maximum on time timer.
If the maximum on time is exceeded before the regulator
output voltage achieves the 1V level, the pulse is terminat-
ed. The GateH pin drives low, and the GateL pin drives
high for the duration of the extended off time. This time is
set by the time out timer and is approximately equal to the
maximum on time, resulting in a 50% duty cycle. The
GateL pin will then drive low, the GateH pin will drive
high, and the cycle repeats.
When regulator output voltage achieves the 1V level pre-
sent at the COMP pin, regulation has been achieved and
normal off time will ensue. The PWM comparator termi-
FB
and V
FFB
pins, as in traditional controllers.
CC1
2
TM
control loop varies switch on
supply pin exceeds the 3.9V
CC1
2
TM
pin exceeds the monitor
method of control
OFF
capacitor. To