XC95144XL-5CS144C Xilinx, XC95144XL-5CS144C Datasheet
XC95144XL-5CS144C
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XC95144XL-5CS144C Summary of contents
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... Pin-compatible with 5V-core XC95144 device in the 100-pin TQFP package Description The XC95144XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns. See Figure 2 overview ...
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... JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 4 I/O/GTS Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95144XL Architecture www.xilinx.com 1-800-255-7778 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...
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... GND Max GND Max Max; CC CCIO V = GND or 3. Min < V < 5. GND 1.0 MHz GND, No load 1.0 MHz IN www.xilinx.com 1-800-255-7778 XC95144XL High Performance CPLD Value –0.5 to 4.0 –0.5 to 5.5 –0.5 to 5.5 –65 to +150 +220 +150 Min Max 3.0 3 3.0 3.6 3.0 3.6 2.3 2.7 0 0.80 2.0 5 ...
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... XC95144XL High Performance CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input PSU T I/O hold time after p-term clock input ...
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... LOGI T Internal low power logic delay LOGILP Feedback Delays T Fast CONNECT II feedback delay F Time Adders T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW DS056 (v1.5) August 21, 2003 Preliminary Product Specification XC95144XL High Performance CPLD XC95144XL-5 XC95144XL-7 Min Max Min Max - 1.5 - 2.3 - 1.1 - 1 ...
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... XC95144XL High Performance CPLD XC95144XL I/O Pins Function Macro- Block cell TQ100 TQ144 CS144 ...
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... B10 132 8 B9 129 8 A9 126 123 8 D8 120 8 A8 117 8 D9 114 8 B7 111 108 8 www.xilinx.com 1-800-255-7778 XC95144XL High Performance CPLD Macro- cell TQ100 TQ144 CS144 N12 L12 M13 L13 K10 8 54 ...
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... XC95144XL High Performance CPLD XC95144XL Global, JTAG and Power Pins Pin Type TQ100 I/O/GCK1 22 I/O/GCK2 23 I/O/GCK3 27 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR 99 TCK 48 TDI 45 TDO 83 TMS 47 V 3.3V 5, 57, 98 CCINT V 2.5V/3.3V 26, 38, 51, 88 CCIO GND 21, 31, 44, 62, 69, 75, 84, 100 No Connects 8 TQ144 ...
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... R Device Part Marking and Ordering Combination Information Device Type Package Speed Operating Range Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC95144XL-5TQ100C 5 ns XC95144XL-5TQ144C 5 ns XC95144XL-5CS144C 5 ns XC95144XL-7TQ100C 7.5 ns XC95144XL-7TQ144C 7.5 ns XC95144XL-7CS144C 7.5 ns XC95144XL-7TQ100I 7.5 ns XC95144XL-7TQ144I 7.5 ns XC95144XL-7CS144I 7.5 ns XC95144XL-10TQ100C 10 ns XC95144XL-10TQ144C 10 ns XC95144XL-10CS144C 10 ns ...
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... XC95144XL High Performance CPLD Revision History The following table shows the revision history for this document. Date Version 10/30/98 1.1 Minor corrections to CS144 pinout table. 11/13/98 1.2 V1.2 minor correction in CS144 pinout table. 06/20/02 1.3 Updated I Component Availability chart.Added additional I Characteristics table. 06/20/03 1.4 Updated T 08/21/03 1.5 Updated Package Device Marking Pin 1 orientation. ...