SAA7113 Philips Semiconductors, SAA7113 Datasheet - Page 22

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SAA7113

Manufacturer Part Number
SAA7113
Description
9-bit video input processor
Manufacturer
Philips Semiconductors
Datasheet

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8.5
The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is further reduced to
1 MHz in a low-pass filter. The sync pulses are sliced and
fed to the phase detectors where they are compared with
the sub-divided clock frequency. The resulting output
signal is applied to the loop filter to accumulate all phase
deviations. Internal signals (e.g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO,
see Fig.19.
The detection of ‘pseudo syncs’ as part of the macrovision
copy protection standard is also done within the
synchronization circuit.
The result is reported as flag COPRO within the decoder
status byte at subaddress 1FH.
Table 1 Clock frequencies
1999 Jul 01
handbook, full pagewidth
9-bit video input processor
LLC2 (internal)
LLC4 (internal)
Synchronization
LLC8 (virtual)
CLOCK
XTAL
LLC
LFCO
BAND PASS
FC = LLC/4
FREQUENCY (MHz)
Fig.20 Block diagram of clock generation circuit.
DETECTION
24.576
3.375
13.5
6.75
CROSS
ZERO
27
DETECTION
PHASE
22
8.6
The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
[6.75 MHz = 429
Internally the LFCO signal is multiplied by a factor of
2 and 4 in the PLL circuit (including phase detector, loop
filtering, VCO and frequency divider) to obtain the output
clock signals. The rectangular output clocks have a 50%
duty factor.
8.7
A missing clock, insufficient digital or analog V
voltages (below 2.8 V) will initiate the reset sequence; all
outputs are forced to 3-state (see Fig.21).
It is possible to force a reset by pulling the Chip Enable
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC and SDA return
from 3-state to active, while RTS0, RTS1 and RTCO
remain in 3-state and have to be activated via I
programming (see Table 2).
Clock generation circuit
Power-on reset and CE input
DIVIDER
FILTER
LOOP
1/2
f
H
(50 Hz) or 432
OSCILLATOR
DIVIDER
1/2
MHB330
Product specification
SAA7113H
f
H
(60 Hz)].
LLC
LLC2
DDA0
2
C-bus
supply

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