RJ80535 Intel, RJ80535 Datasheet - Page 62

• Manufacturer Part Number: RJ80535
• Description: Pentium M Processor
• Manufacturer: Intel

Package Mechanical Specifications and Pin Information
4.2
62
Table 22. Signal Description (Sheet 1 of 7)
Alphabetical Signals Reference
A[31:3]#
A20M#
ADS#
ADSTB[1:0]#
BCLK[1:0]
BNR#
BPM[2:0]#
BPM[3]
BPRI#
BR0#
Name
Output
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Input/
Type
Input
Input
Input
A[31:3]# (Address) define a 2
phase 1 of the address phase, these pins transmit the address of a transaction.
In sub-phase 2, these pins transmit transaction type information. These signals
must connect the appropriate pins of both agents on the Intel Pentium M
processor system bus. A[31:3]# are source synchronous signals and are latched
into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps
which are sampled before RESET# is deasserted.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address
bit 20 (A20#) before looking up a line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M#
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new
transaction.
Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as shown below.
The differential pair BCLK (Bus Clock) determines the system bus frequency. All
processor system bus agents must receive these signals to drive their outputs
and latch their inputs.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent that is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor that indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[3:0]# should connect the appropriate pins of all Intel Pentium
M processor system bus agents.This includes debug or performance monitoring
tools.
Please refer to the platform design guides and ITP700 Debug Port Design Guide
for more detailed information.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
system bus. It must connect the appropriate pins of both processor system bus
agents. Observing BPRI# active (as asserted by the priority agent) causes the
other agent to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
BR0# is used by the processor to request the bus. The arbitration is done
between the Intel Pentium M processor (Symmetric Agent) and the MCH-M
(High Priority Agent) of the Intel 855PM or Intel 855GM chipset.
Signals
REQ[4:0]#, A[16:3]#
A[31:17]#
32
Associated Strobe
ADSTB[0]#
ADSTB[1]#
-byte physical memory address space. In sub-
Description
Intel
®
Pentium
®
M Processor Datasheet