RJ80535 Intel, RJ80535 Datasheet - Page 64

• Manufacturer Part Number: RJ80535
• Description: Pentium M Processor
• Manufacturer: Intel

Package Mechanical Specifications and Pin Information
64
Table 22. Signal Description (Sheet 3 of 7)
DPSLP#
DPWR#
DRDY#
DSTBN[3:0]#
DSTBP[3:0]#
FERR#/PBE#
GTLREF
Name
Output
Output
Output
Output
Input/
Input/
Input/
Type
Input
Input
Input
DPSLP# when asserted on the platform causes the processor to transition from
the Sleep state to the Deep Sleep state. In order to return to the Sleep state,
DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and
also connects to the MCH-M component of the Intel 855PM or Intel 855GM
chipset.
DPWR# is a control signal from the Intel 855PM and Intel 855GM chipsets used
to reduce power on the Intel Pentium M data bus input buffers.
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of both processor system bus agents.
Data strobe used to latch in D[63:0]#.
Data strobe used to latch in D[63:0]#.
FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed
signal and its meaning is qualified by STPCLK#. When STPCLK# is not
asserted, FERR#/PBE# indicates a floating point when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 80387 coprocessor, and is included for compatibility with systems using
MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending break
event waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. When FERR#/PBE# is
asserted, indicating a break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active will also cause an
FERR# break event. For additional information on the pending break event
functionality, including identification of support for the feature and enable/disable
information, refer to Volume 3 of the Intel
Manual and the Intel
application note.
For termination requirements please refer to the platform design guides.
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3 V
if a signal is a logical 0 or logical 1. Please refer to the platform design guides for
details on GTLREF implementation.
Signals
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
Signals
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#

CCP
Processor Identification and CPUID Instruction
. GTLREF is used by the AGTL+ receivers to determine
Associated Strobe
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
Associated Strobe
DSTBP[0]#
DSTBP[1]#
DSTBP[2]#
DSTBP[3]#
Description
Intel
®

Pentium
Architecture Software Developer’s
®
M Processor Datasheet