XC7300FM Xilinx, XC7300FM Datasheet
XC7300FM
Related parts for XC7300FM
XC7300FM Summary of contents
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Features • High-performance Erasable Programmable Logic Devices (EPLDs) – 7.5 ns pin-to-pin speeds on all fast inputs – 167 MHz maximum clock frequency • Advanced Dual-Block architecture – Fast Function Blocks – High-Density Function Blocks (XC7354, ...
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... Designers can operate speed-criti- cal paths at maximum performance, while non-critical paths dissipate less power. Xilinx development software supports XC7300 EPLD design using third-party schematic entry tools, HDL com- pilers, or direct equation-based text files. Using workstation and one of these design capture methods, designs are automatically mapped to an XC7300 EPLD in a matter of minutes ...
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Global 2 Fast OE AND Array 12 from Fast 12 Input Pins 24 3 Inputs from UIM 9 from FFB Macrocell 9 Feedback 5 Private P-Terms per Macrocell Feedback to UIM Pin Feedback to UIM Figure 2. Fast Function ...
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XC7300 EPLD Family The programmable clock source is one of two global Fast- Clock signals (FCLK0 or FCLK1) that are distributed with short delay and minimal skew over the entire chip. The Fast Function Block Macrocells drive chip outputs directly ...
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AND Array 21 Inputs from UIM 3 from Fast Input Pins (FI) 12 Sharable 5 Private P-Terms per P-Terms per Function Block Macrocell More Macrocells Shift-In from Previous MC Shift-Out to Next ...
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Q output identical to the D input, independent of the clock conventional flip-flop. The Macrocell clock source is programmable and can be one of the private product terms or one of two global Fast- CLK ...
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XC7300 EPLD Family Output buffers, except those connected to Fast Function Blocks, can sink 12 mA when V CCIO Block outputs can sink 24 mA when V puts on the XC7318 and XC7336 devices connect to FFBs. Outputs listed as ...
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... Xilinx representative. . XEPLD Development System The designer can create, implement, and verify digital logic circuits for EPLD devices using the Xilinx XEPLD Development System. Designs can be represented as pins should total 1 F schematics consisting of XEPLD library components, as behavioral descriptions mixture of both. The ...
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XC7300 EPLD Family t FOE FOE t I, I/O IN Input Register t SUIN t HIN t CE SUCEIN t HCEIN t COIN FAST t IN INPUT FCLK Figure 8. XC7300 Timing Model Synchronous Clock Switching Characteristics F Pin CLK ...
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Combinatorial Switching Characteristics Input, I/O Pin UIM Delay Logic Delay P-Term Assignment Delay Transparent Register Delay Output Buffer Output Pin Asynchronous Clock Switching Characteristics Input, I/O Pin t IN Input, I/O Delay UIM Delay Clock at Register Data from Logic ...