AD7467BRT AD [Analog Devices], AD7467BRT Datasheet

AD7467BRT

Manufacturer Part Number

AD7467BRT

Description

1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23

Manufacturer

AD [Analog Devices]

Datasheet

1.AD7467BRT.pdf (15 pages)

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GENERAL DESCRIPTION

The AD7466/AD7467/AD7468 are 12/10/8-bit, high

speed, low power, successive-approximation ADCs re-

spectively. The parts operate from a single 1.8 V to 3.6 V

power supply and feature throughput rates up to 100

kSPS. The parts contain a low-noise, wide bandwidth

track/hold amplifier which can handle input frequencies in

excess of 100 kHz.

The conversion process and data acquisition are controlled

using

interface with microprocessors or DSPs. The input signal

is sampled on the falling edge of

also initiated at this point. There are no pipelined delays

associated with the part.

The AD7466/AD7467/AD7468 use advanced design tech-

niques to achieve very low power dissipation at high

throughput rates.

The reference for the part is taken internally from V

This allows the widest dynamic input range to the ADC.

Thus the analog input range for the part is 0 to V

conversion rate is determined by the SCLK.

REV. PrC

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

FEATURES

Specified for V

Low Power:

Fast Throughput Rate: 100 kSPS

Wide Input Bandwidth:

Flexible Power/Serial Clock Speed Management

No Pipeline Delays

High Speed Serial Interface

Standby Mode: 0.5

6-Lead SOT-23 Package and 8 lead SOIC

APPLICATIONS

Battery Powered Systems

Ramote Data Acquisition

Isolated Data Acquisition

70dB SNR at 30 kHz Input Frequency

Medical Instruments

SPI/QSPI/ Wire/DSP Compatible

Preliminary Technical Data

0.9 mW max at 60 kSPS with 3.6 V Supplies

0.4 mW max at 100 kSPS with 1.8 V Supplies

and the serial clock, allowing the devices to

07/01

of 1.8 V to 3.6 V

A max

and the conversion is

pecifications

. The

DD.

8/10/12-Bit ADCs in 6 Lead SOT-23

PRODUCT HIGHLIGHTS

1. Specified for Supply voltages of 1.8 V to 3.6 V

2. 8/10/12-Bit ADCs in a SOT-23 package.

3. High Throughput with Low Power Consumption

4. Flexible Power/Serial Clock Speed Management

5. Reference derived from the power supply.

6. No Pipeline Delay

V IN

One Technology Way, P .O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

The conversion rate is determined by the serial clock

allowing the conversion time to be reduced through the

serial clock speed increase. Automatic power down after

conversion, which allows the average power cunsumption

to be reduced when in powerdown. Power consumption

is 0.5 A max when in powerdown.

The part features a standard successive-approximation

ADC with accurate control of the conversions via a

input.

AD7466/67/68

AD7466/AD7467/AD7468

FUNCTIONAL BLOCK DIAGRAM

T/H

World Wide Web Site: http://www.analog.com

GND

1.8 V, Micro-Power,

APPROXIMATION

CONTROL LOGIC

SUCCESSIVE

12/10/8-BIT

ADC

V DD

Analog Devices, Inc., 2001

SCLK

SDATA

Related parts for AD7467BRT

AD7467BRT Summary of contents

Page 1

Preliminary Technical Data FEATURES Specified for Low Power: 0.9 mW max at 60 kSPS with 3.6 V Supplies 0.4 mW max at 100 kSPS with 1.8 V Supplies Fast Throughput Rate: 100 ...

AD7466–SPECIFICATIONS Parameter DYNAMIC PERFORMANCE 2 Signal-to-Noise + Distortion (SINAD) 2 Signal-to-Noise Ratio (SNR) 2 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) 2 Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power ...

Page 3

AD7467–SPECIFICATIONS Parameter DYNAMIC PERFORMANCE 2 Signal-to-Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) 2 Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth ...

Page 4

AD7468–SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) 2 Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth 2 ...

Page 5

TIMING SPECIFICATIONS Parameter AD7466 Units kHz min SCLK MHz max t 16* t CONVERT SCLK min quiet min min ...

Page 6

... AD7468 consists of four leading zeros followed by 8 bits of data. 4 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7466/AD7467/AD7468 conver- sion process. Model AD7466BRT AD7467BRT AD7468BRT AD7466BRM AD7467BRM AD7468BRM 3 EVAL-AD7466CB 3 ...

Page 7

TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line pass- ing through the endpoints of the ADC transfer function. For the AD7466/67/68 the endpoints of the transfer function are zero scale, a point 1 LSB below the ...

Page 8

AD7466/AD7467/AD7468 AD7466/AD7467/AD7468 TYPICAL CURVES Figure 2 shows a typical FFT plot for the AD7466 at 100 kHz sample rate and 30 kHz input frequency TITLE Figure 2. AD7466 Dynamic Performance at 100 ...

Page 9

CIRCUIT INFORMATION The AD7466/AD7467/AD7468 are fast, micro-power, 12/ 10/8-bit, A/D converters respectively. The parts can be operated from a +1 +3.6 V supply. When operated from any supply voltage within this range, the AD7466/ AD7467/AD7468 is capable of ...

Page 10

AD7466/AD7467/AD7468 TYPICAL CONNECTION DIAGRAM Figure 11 shows a typical connection diagram for the AD7466/AD7467/AD7468 taken internally from REF V and as such V should be well decoupled. This pro vides an analog input range of 0V ...

Page 11

TITLE Figure 13. THD vs. Analog Input Frequency for Various Source Impedance Digital Inputs The digital inputs applied to the AD7466/AD7467/ AD7468 are not limited by the maximum ratings which limit the analog ...

Page 12

AD7466/AD7467/AD7468 SERIAL INTERFACE Figure 15, 16, 17 show the detailed timing diagram for serial interfacing to the AD7466/AD7467/AD7468.The serial clock provides the conversion clock and also con- trols the transfer of information from the ADC during a conversion. On the ...

Page 13

MICROPROCESSOR INTERFACING The serial interface on the AD7466/AD7467/AD7468 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7466/AD7467/AD7468 with some of the more common microcontroller and DSP serial ...

Page 14

AD7466/AD7467/AD7468 AD7466/7/8* SCLK SDATA *Additional Pins omitted for clarity Figure 20. Interfacing to the DSP56xx AD7466/67/68 to MC68HC16 The Serial Peripheral Interface (SPI) on the MC68HC16 is configured for Master Mode (MSTR = 1), Clock Po- larity Bit (CPOL) = ...

Page 15

REV. PrC pecifications OUTLINE ...

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