CY7C1214F-100AC CYPRESS [Cypress Semiconductor], CY7C1214F-100AC Datasheet - Page 12

• Manufacturer Part Number: CY7C1214F-100AC
• Description: 1-Mb (32K x 32) Flow-Through Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05434 Rev. *A
Timing Diagrams
Read/Write Timing
Notes:
18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed.
19. GW is HIGH
BWE, BW
Data Out (Q)
Data In (D)
ADDRESS
ADSP
ADSC
ADV
CLK
[A:D]
OE
CE
A1
High-Z
[16, 18, 19]
t ADS
(continued)
t CES
t AS
Q(A1)
Back-to-Back READs
A2
t ADH
t CEH
t
t AH
CH
t CYC
t
CL
Q(A2)
t
OEHZ
A3
Single WRITE
t
t DS
WES
D(A3)
t DH
t
WEH
DON’T CARE
A4
t OELZ
t CDV
Q(A4)
UNDEFINED
Q(A4+1)
BURST READ
Q(A4+2)
Q(A4+3)
CY7C1214F
D(A5)
A5
Back-to-Back
Page 12 of 15
WRITEs
D(A6)
A6