CY7C1214F-100AC CYPRESS [Cypress Semiconductor], CY7C1214F-100AC Datasheet - Page 8

• Manufacturer Part Number: CY7C1214F-100AC
• Description: 1-Mb (32K x 32) Flow-Through Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05434 Rev. *A
Thermal Resistance
Capacitance
AC Test Loads and Waveforms
Switching Characteristics
Θ
Θ
C
C
C
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Notes:
10. Timing reference level is 1.5V when V
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12. This part has a voltage regulator internally; t
13. t
14. At any given voltage and temperature, t
15. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
9. Tested initially and after any design or process change that may affect these parameters.
JA
Parameter
JC
IN
CLK
I/O
OUTPUT
Parameter
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
3.3V I/O Test Load
, t
CLZ
,t
OELZ
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
, and t
[9]
Z
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
DD
0
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
= 50Ω
(Typical) to the First Access
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
(a)
V
[9]
Description
L
Description
= 1.5V
[13, 14, 15]
[13, 14, 15]
R
DDQ
L
OEHZ
Over the Operating Range
= 50Ω
= 3.3V.
POWER
is less than t
OUTPUT
3.3V
[13, 14, 15]
Description
INCLUDING
[13, 14, 15]
is the time that the power needs to be supplied above V
JIG AND
SCOPE
[12]
OELZ
T
V
V
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
5 pF
A
DD
DDQ
and t
= 25°C, f = 1 MHz,
= 3.3V.
= 3.3V
CHZ
(b)
is less than t
R = 317Ω
[10, 11]
Test Conditions
R = 351Ω
Test Conditions
CLZ
to eliminate bus contention between SRAMs when sharing the same
GND
V
DDQ
≤ 1 ns
Min.
8.5
3.0
3.0
2.0
DD
1
0
0
117 MHz
(minimum) initially before a Read or Write operation
10%
Max.
ALL INPUT PULSES
7.5
3.5
3.5
3.5
90%
TQFP Package
Min.
4.0
4.0
2.0
Max.
(c)
10
1
0
0
100 MHz
5
5
5
41.83
9.99
CY7C1214F
Max.
8.5
3.5
3.5
3.5
Page 8 of 15
90%
10%
Unit
pF
pF
pF
≤ 1 ns
°C/W
°C/W
Unit
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns