CAT25M01 ONSEMI [ON Semiconductor], CAT25M01 Datasheet - Page 6

• Manufacturer Part Number: CAT25M01
• Description: 1 Mb SPI Serial CMOS EEPROM
• Manufacturer: ONSEMI [ON Semiconductor]

Write Operations
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
The CAT25M01 device powers up into a write disable
SCK
SCK
CS
SO
CS
SO
SI
SI
Note: Dashed Line = mode (1, 1)
Note: Dashed Line = mode (1, 1)
0
0
Figure 3. WREN Timing
Figure 4. WRDI Timing
0
0
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0
0
HIGH IMPEDANCE
0
HIGH IMPEDANCE
0
6
0
0
Write Enable and Write Disable
Status Register WEL bit are set by sending the WREN
instruction to the CAT25M01. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior any WRITE or WRSR instruction.
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
1
The internal Write Enable Latch and the correspon–ding
The internal write enable latch is reset by sending the
1
1
0
0
0