ADF4196BCPZ AD [Analog Devices], ADF4196BCPZ Datasheet
ADF4196BCPZ
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ADF4196BCPZ Summary of contents
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Data Sheet FEATURES Fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 μs with phase settled within 20 μs 1 degree rms phase error at 4 GHz RF output Digitally programmable output ...
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ADF4196 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 Transistor ...
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Data Sheet SPECIFICATIONS SDV 2.4 kΩ; dBm referred to 50 Ω; T SET A Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RF ) ...
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ADF4196 Parameter SW1, SW2, AND SW3 On Resistance SW1 and SW2 SW3 NOISE CHARACTERISTICS Output 900 MHz 2 1800 MHz 3 Phase Noise Normalized Phase Noise Floor ( SYNTH Normalized 1/f Noise ( 1_f Choose a ...
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Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating AV to Ground −0 +3 SDV −0 +0 ...
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ADF4196 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CMR Common-Mode Reference Voltage for the Output Voltage Swing of the Differential Amplifier. Internally biased to three-fifths Differential Amplifier Output. ...
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Data Sheet Pin No. Mnemonic Description 23 R Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at SET the R pin is 0.55 V. The relationship between I SET . ...
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ADF4196 TYPICAL PERFORMANCE CHARACTERISTICS FREQ. UNIT GHz KEYWORD R PARAM TYPE S IMPEDANCE 50 DATA FORMAT MA FREQ. MAGS11 ANGS11 FREQ. 0.5 0.8897 –16.6691 2.3 0.6 0.87693 –19.9279 2.4 0.7 0.85834 –23.561 2.5 0.8 0.85044 –26.9578 2.6 0.9 0.83494 –30.8201 ...
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Data Sheet TUNE 3 CP OUT OUT– DCS1800 Tx SETUP, 60kHz LOOP BW. 1 MEASURED ON EVAL-ADF4193EBZ1 EVALUATION BOARD. TIMERS 28, SW1/SW2, SW3 = 35. CP FREQUENCY LOCK IN WIDE BW MODE @ ...
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ADF4196 1000 100 7nV 20kHz 10k 100k FREQUENCY (Hz) Figure 16. Voltage Noise Density Measured at the Differential Amplifier Output 100 SW3 90 +85°C SW1, 80 SW2 +85°C +25°C 70 +25°C –40° –40°C ...
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Data Sheet THEORY OF OPERATION GENERAL DESCRIPTION The ADF4196 is targeted at GSM base station requirements, specifically to eliminate the need for ping-pong solutions. It can also be used in pulse Doppler radar applications. The ADF4196 works on the basis ...
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ADF4196 PFD AND CHARGE PUMP The PFD takes inputs from the R divider and N divider and produces up and down outputs with a pulse width difference that is proportional to the phase difference between the inputs. The charge pump ...
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Data Sheet DIFFERENTIAL AMPLIFIER The internal, low noise, differential-to-single-ended amplifier converts the differential charge pump output to a single-ended control voltage for the tuning port of the VCO. Figure 26 shows a simplified schematic of the differential amplifier. The output ...
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ADF4196 REGISTER MAP 9-BIT RF INT VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DBB DBB DBB 4-BIT RF R COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 ...
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Data Sheet FRAC/INT REGISTER (R0) LATCH MAP 9-BIT RF INT VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 ...
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ADF4196 MOD/R REGISTER (R1) LATCH MAP 4-BIT RF R COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 REF/2 0 DISABLED 1 ENABLED F2 PRESCALER F1 DOUBLER ENABLE 0 4/5 0 DOUBLER DISABLED ...
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Data Sheet PHASE REGISTER (R2) BIT LATCH MAP DB15 DB14 DB13 0 P12 P11 P12 ≤ PHASE VALUE < MOD 1 R2, the phase register, is used to program ...
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ADF4196 FUNCTION REGISTER (R3) LATCH MAP DB15 DB14 DB13 R3, the function register, needs to be programmed only during the initialization sequence (see Table 9). Control Bits Register R3 is selected with C3, C2, and C1 set ...
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Data Sheet CHARGE PUMP REGISTER (R4) LATCH MAP RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 R4, the charge pump register, is used for programming the timers for loop filter switches. These switches ...
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ADF4196 POWER-DOWN REGISTER (R5) BIT MAP R5, the power-down register, can be used to power down the PLL and differential amplifier sections. After power is initially applied, Register R5 must be programmed to clear the power-down bits. Then, before the ...
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Data Sheet MUX REGISTER (R6) LATCH MAP AND TRUTH TABLE SIGMA-DELTA AND LOCK DETECT MODES DB15 DB14 DB13 DB12 M13 M12 M11 M10 M13 M12 M11 ALL OTHER STATES R6, the ...
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ADF4196 PROGRAMMING THE ADF4196 The ADF4196 can synthesize output frequencies with a channel step or resolution that is a fraction of the input reference fre- quency. For a given input reference frequency and a desired output frequency step, the first ...
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Data Sheet Reference Spurs Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feedthrough mechanism that bypasses the loop can cause a problem. One such mechanism ...
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ADF4196 Phase Lookup Table The fast lock sequence of the ADF4196 write to Register R0. The fast lock timers are programmed so that after the PLL has settled into wide bandwidth mode, the charge pump current is reduced and the ...
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Data Sheet APPLICATIONS INFORMATION LOCAL OSCILLATOR FOR A GSM BASE STATION Figure 37 shows the ADF4196 being used with a VCO to produce the LO for a GSM1800 base station. For GSM, the REF signal can be any integer multiple ...
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ADF4196 ADIsimPLL Support The ADF4193 loop filter design is supported on ADIsimPLL v2.7 or later. Example files for popular applications are available for download from the ADF4193 and ADF4196 + 10µF 100nF 100nF 15 SDV DV DD 100pF 6 RF ...
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Data Sheet INTERFACING The ADF4196 has a simple SPI-compatible serial interface for writing to the device. The CLK, DATA, and LE pins control the data transfer. When LE goes high, the 24 bits that have been clocked into the input ...
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... SEATING PLANE ORDERING GUIDE Model 1, 2 Temperature Range ADF4196BCPZ −40°C to +85°C ADF4196BCPZ-RL7 −40°C to +85°C EVAL-ADF4193EBZ1 EVAL-ADF4193EBZ2 Z = RoHS Compliant Part The EVAL-ADF4193EBZ1 and EVAL-ADF4193EBZ2 evaluation boards are designed to accommodate either the ADF4193 or the ADF4196. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...