MC74HC161 ONSEMI [ON Semiconductor], MC74HC161 Datasheet - Page 6

• Manufacturer Part Number: MC74HC161
• Description: Presettable Counters
• Manufacturer: ONSEMI [ON Semiconductor]

counters that feature parallel Load, synchronous or
asynchronous Reset, a Carry Output for cascading and
count–enable controls.
asynchronous Reset and synchronous Reset, respectively.
INPUTS
Clock (Pin 2)
advances with the rising edge of the Clock input. In addition,
control functions, such as resetting and loading occur with
the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
Data on these pins may be synchronously loaded into the
internal flip–flops and appear at the counter outputs. P0 (Pin
3) is the least–significant bit and P3 (Pin 6) is the
most–significant bit.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
least–significant bit and Q3 (Pin 11) is the most–significant
bit.
Ripple Carry Out (Pin 15)
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Ripple
Carry Out remains high only during the maximum count
state. The logic equation for this output is:
CONTROL FUNCTIONS
Resetting
flip–flops and sets the outputs (Q0 through Q3) to a low
The HC161A/163A are programmable 4–bit synchronous
The HC161A and HC163A are binary counters with
The internal flip–flops toggle and the output count
These are the data inputs for programmable counting.
These are the counter outputs. Q0 (Pin 14) is the
When the counter is in its maximum state 1111, this output
A low level on the Reset pin (Pin 1) resets the internal
Ripple Carry Out = Enable T Q0 Q1 Q2 Q3
15
14
13
12
0
OUTPUT STATE DIAGRAMS
MC74HC161A, MC74HC163A
FUNCTION DESCRIPTION
11
1
Binary Counters
http://onsemi.com
10
2
6
level. The HC161A resets asynchronously, and the HC163A
resets with the rising edge of the Clock input (synchronous
reset).
Loading
9) loads the data from the Preset Data input pins (P0, P1, P2,
P3) into the internal flip–flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load
is low.
Count Enable/Disable
Enable P (Pin 7) and Enable T (Pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:
inputs according to Table 1. In general, Enable P is a
count–enable control: Enable T is both a count–enable and
a Ripple–Carry Output control.
*Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.
Load
3
9
With the rising edge of the Clock, a low level on Load (Pin
These devices have two count–enable control pins:
The count is either enabled or disabled by the control
H
X
X
L
Count Enable = Enable P Enable T Load
Control Inputs
Enable P
4
5
6
7
8
H
H
X
L
Table 1. Count Enable/Disable
Enable T
H
H
H
L
Q0 – Q3
Count
Count
Count
Count
No
No
No
Result at Outputs
High when Q0–Q3
High when Q0–Q3
are maximum*
High when Q0–Q3
are maximum*
Ripple Carry Out
L