PCF8562TT-2 NXP [NXP Semiconductors], PCF8562TT-2 Datasheet
PCF8562TT-2
Related parts for PCF8562TT-2
PCF8562TT-2 Summary of contents
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... C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). 2. Features and benefits AEC-Q100 compliant (PCF8562TT/S400/2) for automotive applications Single chip LCD controller and driver Selectable backplane drive configuration: static backplane multiplexing ...
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... TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm Marking codes All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 June 2011 PCF8562 Universal LCD driver for low multiplex rates Marking code PCF8562TT PCF8562TT/S400 © NXP B.V. 2011. All rights reserved. Version SOT362-1 SOT362 ...
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NXP Semiconductors 5. Block diagram 21 V LCD LCD BIAS GENERATOR CLK CLOCK SELECT 12 AND TIMING SYNC 15 OSC OSCILLATOR SCL INPUT 10 FILTERS SDA Fig 1. Block diagram of PCF8562 ...
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... LCD BP0 22 23 BP2 24 BP1 Top view. For mechanical details, see Pinning diagram for TSSOP48 (PCF8562TT) All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 June 2011 Universal LCD driver for low multiplex rates 48 S22 47 S21 46 S20 45 S19 ...
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NXP Semiconductors 6.2 Pin description Table 3. Symbol SDA SCL SYNC CLK V DD OSC SA0 LCD BP0 to BP3 S0 to S22, S23 to S31 PCF8562 Product data sheet Pin description Pin Type ...
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NXP Semiconductors 7. Functional description The PCF8562 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see can directly drive any static or multiplexed LCD containing up ...
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NXP Semiconductors Fig 4. The host microcontroller maintains the 2-line I PCF8562. The internal oscillator is enabled by connecting pin OSC to pin V appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required ...
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NXP Semiconductors Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought measurement of contrast. Table 5. LCD drive mode static 1:2 multiplex ...
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NXP Semiconductors Using Equation 1 ⁄ bias ⁄ bias is 2 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ...
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NXP Semiconductors Fig 5. PCF8562 Product data sheet 100 % OFF SEGMENT Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 ...
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NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment (Sn) drive waveforms for this mode are shown ...
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NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8562 allows the use of Figure 8. Fig 7. PCF8562 Product data sheet 1 1 ⁄ bias or ⁄ ...
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NXP Semiconductors Fig 8. PCF8562 Product data sheet V LCD 2V /3 LCD BP0 V /3 LCD LCD 2V /3 LCD BP1 V /3 LCD LCD 2V /3 LCD LCD ...
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NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Fig 9. PCF8562 Product data sheet Figure 9. V LCD 2V /3 LCD BP0 V /3 ...
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NXP Semiconductors 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 Fig 10. Waveforms for ...
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NXP Semiconductors 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to ...
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NXP Semiconductors 7.10 Display RAM The display RAM is a static 32 4-bit RAM which stores LCD data. There is a one-to-one correspondence between • the bits in the RAM bitmap and the LCD elements • the RAM columns ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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NXP Semiconductors The following applies to • In static drive mode the eight transmitted data bits are placed in row 0 as one byte. • In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into ...
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NXP Semiconductors 7.10.3 RAM writing in 1:3 multiplex drive mode In 1:3 multiplex drive mode, the RAM is written as shown in well). Table 6. Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display. Display ...
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NXP Semiconductors • In 1:2 multiplex mode, rows 0 and 1 are selected • In static mode, row 0 is selected The PCF8562 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static ...
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NXP Semiconductors 7.12 Command decoder The command decoder identifies command bytes that arrive on the I commands available to the PCF8562 are defined in Table 9. Command Bit mode-set load-data-pointer device-select bank-select blink-select [1] Not used. All available commands carry ...
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NXP Semiconductors Table 11. Bit [1] The possibility to disable the display allows implementation of blinking under external control. [2] Not applicable for static drive mode. Table 12. Bit 7 6, ...
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NXP Semiconductors Table 14. Bit [1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. Table 15. Bit [1] Normal blinking is ...
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NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must be ...
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NXP Semiconductors SDA SCL Fig 15. System configuration 8.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • ...
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NXP Semiconductors 2 8.5 I C-bus controller The PCF8562 acts transmit data the acknowledge signals of the selected devices. Device selection depends on the 2 I C-bus slave address, on the transferred command data ...
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NXP Semiconductors After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and ...
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NXP Semiconductors 9. Internal circuitry Fig 19. Device protection circuits PCF8562 Product data sheet Universal LCD driver for low multiplex rates V DD SA0 CLK OSC SYNC V ...
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NXP Semiconductors 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 16. In accordance with the Absolute Maximum Rating System ...
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NXP Semiconductors 11. Static characteristics Table 17. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I ...
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NXP Semiconductors 12. Dynamic characteristics Table 18. Dynamic characteristics Symbol Parameter Clock f internal clock frequency clk(int) f external clock frequency clk(ext) t HIGH-level clock time ...
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NXP Semiconductors BP0 to BP3, and S0 to S31 Fig 20. Driver timing waveforms SDA SCL SDA Fig 21. I PCF8562 Product data sheet 1/f clk t clk(H) CLK SYNC t PD(SYNC_N BUF LOW t HD;STA 2 C-bus ...
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NXP Semiconductors 13. Application information 13.1 Multiple chip operation For large display configurations or for more segments (> 128 elements) to drive please refer to the PCF8576D device. The contact resistance between the SYNC input/output on each cascaded device must ...
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NXP Semiconductors 15. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. ...
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NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent ...
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NXP Semiconductors 17.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the ...
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NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 22. Acronym CMOS CDM HBM ITO LCD LSB MM MSB ...
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NXP Semiconductors 19. References [1] AN10365 — Surface mount reflow soldering description [2] AN10853 — ESD and EMC sensitivity of IC [3] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [4] IEC 61340-5 — ...
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NXP Semiconductors 20. Revision history Table 23. Revision history Document ID Release date PCF8562 v.6 20110616 • Modifications: Added design-in and replacement part information • Added PCF8562_5 20100519 PCF8562_4 20090318 PCF8562_3 20081202 PCF8562_2 20070122 PCF8562_1 20050801 PCF8562 Product data sheet ...
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NXP Semiconductors 21. Legal information 21.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 22. Contact information For more information, please visit: For sales ...
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NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...