PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 64
PCF8811U/2DA/1
Manufacturer Part Number
PCF8811U/2DA/1
Description
80 x 128 pixels matrix LCD driver
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCF8811U2DA1.pdf
(81 pages)
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NXP Semiconductors
Table 34.
V
[1]
PCF8811_4
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
C
t
t
t
V
V
SCL
SU;STA
HD;STA
LOW
HIGH
SU;DAT
HD;DAT
r
f
SU;STO
SP
BUF
Fig 44. Serial interface timing; 3-line serial interface (read mode)
DD1
nL
nH
b
All specified timings are based on 20 % and 80 % of V
= 1.8 V to 3.3 V; V
SDATA
SCLK
SDO
Parameter
SCL clock frequency
set-up time for a repeated START condition
hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
data set-up time
data hold time
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
set-up time for STOP condition
pulse width of spikes that must be
suppressed by the input filter
bus free time between a STOP and START
condition
noise margin at the LOW level
noise margin at the HIGH level
SCE
I
2
C-bus characteristics; F/S-mode
16.3 I
SS
2
= 0 V; V
C-bus interface timing characteristics
LCD
9 V; T
t
H1
amb
Rev. 04 — 27 June 2008
= 40 C to +85 C; unless otherwise specified
DD
.
Conditions
for each connected device
(including hysteresis)
for each connected device
(including hysteresis)
t
1
t
4
80 x 128 pixels matrix LCD driver
Min
0
600
600
1300
600
100
0
20 + 0.1C
20 + 0.1C
-
600
-
1300
0.1V
0.2V
t
DD1
DD1
3
[1]
b
b
; see
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PCF8811
© NXP B.V. 2008. All rights reserved.
Figure
001aai354
Max
400
-
-
-
-
-
900
300
300
400
-
50
-
-
-
t
S1
45.
64 of 81
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
ns
ns
V
V
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