AD73411BB-80 AD [Analog Devices], AD73411BB-80 Datasheet
AD73411BB-80
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AD73411BB-80 Summary of contents
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GENERAL DESCRIPTION The AD73411 is a single device incorporating a single analog front end (AFE) and a microcomputer optimized for digital signal processing (DSP) and other high-speed numeric processing applications. The AD73411’s analog front end (AFE) section is suitable ...
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AD73411–SPECIFICATIONS Parameter AFE SECTION REFERENCE REFCAP Absolute Voltage, V REFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT ADC SPECIFICATIONS 2, 3 Maximum Input Range at VIN Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = ...
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Parameter DAC SPECIFICATIONS (Continued) Power Supply Rejection 4, 5 Group Delay 2, 7 Output DC Offset LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current IH LOGIC OUTPUT V , Output ...
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AD73411–SPECIFICATIONS Parameter DSP SECTION V Hi-Level Input Voltage IH V Hi-Level CLKIN Voltage IH V Lo-Level Input Voltage IL V Hi-Level Output Voltage OH V Lo-Level Output Voltage OL I Hi-Level Input Current IH I Lo-Level Input Current IL I ...
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POWER CONSUMPTION Parameter Typ AFE SECTION ADC Only On 7 ADC and DAC On 11 REFCAP Only On 0.65 REFCAP and 2.7 REFOUT Only On All AFE Sections Off 0.6 5 µA All AFE Sections Off DSP SECTION Idle Mode ...
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... PBGA, θ Thermal Impedance . . . . . . . . . . . . . . . . . 25°C/W JA Temperature Model Range AD73411BB-80 –20°C to +85°C AD73411BB-40 –20°C to +85°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73411 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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BGA Mnemonic Location Function VINP T1 This pin allows direct access to the positive input of the sigma-delta modulator. VINN T3 This pin allows direct access to the negative input of the sigma-delta modulator. REFOUT R7 Buffered Reference Output, which ...
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AD73411 PBGA BALL FUNCTION DESCRIPTIONS (Continued) BGA Mnemonic Location Function IRQL0/ (Input) Level-Sensitive Interrupt Requests PF5 B1 (Input/Output) Programmable I/O Pin. IRQE/ (Input) Edge-Sensitive Interrupt Requests PF4 A1 (Input/Output) Programmable I/O Pin. PF3 H4 (Input/Output) Programmable I/O Pin During Normal ...
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ARCHITECTURE OVERVIEW The AD73411 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single pro- cessor cycle. The AD73411 assembly language uses an algebraic syntax ...
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AD73411 AVDD1 ANALOG VINP LOOPBACK/ 0/38dB SINGLE-ENDED ENABLE VINN VOUTP CONTINUOUS +6/–15dB TIME PGA LOW-PASS FILTER VOUTN REFCAP REFERENCE REFOUT AGND1 The AFE is configured as a single I/O channel (similar to that of the discrete AD73311L; refer to the ...
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Analog Sigma-Delta Modulator The AD73411 input channel employs a sigma-delta conver- sion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. Sigma-delta converters employ a technique known as over- sampling, where the sampling rate is ...
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AD73411 ADC Coding The ADC coding scheme is in twos complement format (see Figure 5). The output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit ...
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SPORT2 Overview SPORT2 is a flexible, full-duplex, synchronous serial port whose protocol has been designed to allow extra AFE devices (AD733xx series maximum of eight I/O channels connected in cascade to a DSP SPORT (0 ...
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AD73411 MCLK (EXTERNAL) SE RESET SDIFS SDI 8 CONTROL REGISTER A Sample Rate Divider The AD73411 features a programmable sample rate divider that allows users flexibility in matching the codec’s ADC and DAC sample rates to the needs of the ...
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Address (Binary) Name 000 CRA 001 CRB 010 CRC 011 CRD 100 CRE 101 CRF 110 to 111 ...
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AD73411 CONTROL REGISTER B 7 CEE Bit CONTROL REGISTER C 7 RES Bit CONTROL REGISTER D 7 MUTE Bit ...
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CONTROL REGISTER E 7 RES Bit CONTROL REGISTER F 7 ALB Bit Table XIII. Control Register E Description RES ...
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AD73411 AFE Operating Modes Five operating modes are available on the AFE. Two of these— Digital Loop-Back and Sport Loop-Back—are provided as diagnostic modes with the other three, Program, Data and Mixed Program/Data, being available for general-purpose use. The device ...
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SE SCLK SDOFS SDO SAMPLE WORD (DEVICE 1) SDIFS SDI DATA (CONTROL) WORD (DEVICE 1) SE SCLK SDOFS(2) SDO(2) SAMPLE WORD (DEVICE 2) SDOFS(1) SDIFS(2) SDO(1) SAMPLE WORD (DEVICE 1) SDI(2) SDIFS(1) SDI(1) DATA (CONTROL) WORD (DEVICE 2) SAMPLE WORD ...
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AD73411 ANALOG LOOP-BACK SELECT VINP VINN VOUTP CONTINUOUS +6/–15dB LOW-PASS PGA VOUTN FILTER REFOUT REFERENCE REFCAP AFE Interfacing The AFE section SPORT (SPORT2) can be interfaced to either SPORT0 or SPORT1 of the DSP section. Both serial input and output ...
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In Cascade Mode, each device must know the number of devices in the cascade because the Data and Mixed modes use a method of counting input frame sync pulses to decide when they should update the DAC register from the ...
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AD73411 The AD73411 can respond to eleven interrupts. There can six external interrupts (one edge-sensitive, two level- sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port ...
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Terminating Unused Pin The following chart shows the recommendations for terminating unused pins. Pin Terminations I/O Hi-Z Pin 3-State Reset Caused Name (Z) State By XTAL I I CLKOUT O O BR, EBR A13 (Z) Hi-Z IS IAD12:0 ...
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AD73411 are twelve levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global enable or dis- able servicing of the interrupts (including power-down), regardless of the state of IMASK. Disabling the interrupts does not affect serial ...
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FULL MEMORY MODE AD73411 14 1/2x CLOCK ADDR13–0 CLKIN OR XTAL CRYSTAL 24 FL0–2 DATA23–0 PF3 BMS IRQ2/PF7 IRQE/PF4 IRQL0/PF5 WR IRQL1/PF6 RD MODE C/PF2 MODE B/PF1 IOMS MODE A/PF0 SPORT1 SCLK1 AFE* RFS1 OR IRQ0 SECTION TFS1 OR IRQ1 ...
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AD73411 MODE C MODE B MODE NOTES 1 All mode pins are recognized while RESET is active (low). 2 When Mode ...
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DATA MEMORY ALWAYS ACCESSIBLE AT ADDRESS 0x2000 – 0x3FFF 0x0000– INTERNAL MEMORY 0x1FFF ACCESSIBLE WHEN DMOVLAY = 0 0x0000– 0x1FFF 0x0000– ACCESSIBLE WHEN 0x1FFF DMOVLAY = 1 EXTERNAL ACCESSIBLE WHEN MEMORY DMOVLAY = 2 Data Memory (Host Mode) allows access ...
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AD73411 Table XXII. Data Formats Internal BTYPE Memory Space Word Size 00 Program Memory 24 01 Data Memory 16 10 Data Memory 8 11 Data Memory 8 Unused bits in the 8-bit data memory formats are filled with 0s. The ...
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When BDMA booting is specified, the BDMA interface is set up during reset to the following defaults: the BDIR, BMPAGE, BIAD and BEAD registers are set to 0, the BTYPE register is set specify program memory 24-bit ...
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AD73411 of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. One method of ensuring that the values located on the mode pins are those desired construct a circuit ...
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Target System Interface Signals When the EZ-ICE board is installed, the performance on some system signals changes. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: • EZ-ICE emulation introduces an ...
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AD73411 ANTIALIAS FILTER 100 VINP 0.047 F 0.047 F VINN 100 VOUTP CONTINUOUS +6/–15dB LOW-PASS PGA VOUTN REFOUT REFERENCE REFCAP 0.1 F Analog Inputs The analog input (encoder) section of the AD73411 can be inter- faced to external circuitry in ...
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F 100 VINP 0.047 10k F VINN VOUTP CONTINUOUS +6/–15dB LOW-PASS PGA VOUTN REFOUT REFERENCE REFCAP 0.1 F VINP 0.1 F 100 VINN 0.047 10k F VOUTP CONTINUOUS +6/–15dB LOW-PASS PGA VOUTN REFOUT REFERENCE REFCAP 0.1 F Interfacing to ...
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AD73411 Differential-to-Single-Ended Output In some applications it may be desirable to convert the full differential output of the decoder channel to a single-ended signal. The circuit of Figure 33 shows a scheme for doing this. VINP VINN R F VOUTP ...
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Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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AD73411 0.089 (2.27) 0.073 (1.85) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 119-Ball Plastic Ball Grid Array (PBGA) B-119 0.300 (7.62) BSC 0.559 (14.20) BOTTOM 0.543 (13.80) VIEW 0.050 0.874 (22.20) ...