MAXQ61CA MAXIM [Maxim Integrated Products], MAXQ61CA Datasheet - Page 13

• Manufacturer Part Number: MAXQ61CA
• Description: 16-Bit Microcontroller with Infrared Module
• Manufacturer: MAXIM [Maxim Integrated Products]

Table 1. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
The device provides a soft stack that can be used to
store program return addresses (for subroutine calls
and interrupt handling) and other general-purpose data.
This soft stack is located in the 2KB SRAM data mem-
ory, which means that the SRAM data memory must be
shared between the soft stack and general-purpose
application data storage. However, the location and
size of the soft stack is determined by the user, provid-
ing maximum flexibility when allocating resources for a
particular application. The stack is used automatically
by the processor when the CALL, RET, and RETI instruc-
tions are executed and when an interrupt is serviced. An
application can also store and retrieve values explicitly
using the stack by means of the PUSH, POP, and POPI
instructions.
The SP pointer indicates the current top of the stack,
which initializes by default to the top of the SRAM data
memory. As values are pushed onto the stack, the SP
pointer decrements, which means that the stack grows
downward towards the bottom (lowest address) of the
data memory. Popping values off the stack causes the
SP pointer value to increase. Refer to the MAXQ610
User’s Guide for more details.
The utility ROM is a 1.5KB block of internal ROM memory
located in program space beginning at address 8000h.
This ROM includes the following routines:
• Production test routines (internal memory tests,
• User-callable routines for buffer copying and fast table
Following any reset, execution begins in the utility ROM
at address 8000h. At this point, unless test mode has
been invoked (which requires special programming
through the JTAG interface), the utility ROM in the device
memory loader, etc.), which are used for internal
testing only, and are generally of no use to the end-
application developer
lookup (more information on these routines can be
found in the MAXQ610 User’s Guide)
WD[1:0]
00
01
10
11
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________
WATCHDOG CLOCK
Sysclk/2
Sysclk/2
Sysclk/2
Sysclk/2
15
18
21
24
Stack Memory
Utility ROM
WATCHDOG INTERRUPT TIMEOUT
174.7ms
21.9ms
2.7ms
1.4s
always automatically jumps to location 0000h, which is
the beginning of user application code.
The internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the applica-
tion software. If software is operating correctly, the coun-
ter is periodically reset and never reaches its maximum
count. However, if software operation is interrupted,
the timer does not reset, triggering a system reset and
optionally a watchdog timer interrupt. This protects the
system against electrical noise or electrostatic discharge
(ESD) upsets that could cause uncontrolled processor
operation. The internal watchdog timer is an upgrade to
older designs with external watchdog devices, reducing
system cost and simultaneously increasing reliability.
The watchdog timer functions as the source of both the
watchdog timer timeout and the watchdog timer reset.
The timeout period can be programmed in a range of
2
ated when the timeout period expires if the interrupt
is enabled. All watchdog timer resets follow the pro-
grammed interrupt timeouts by 512 system clock cycles.
If the watchdog timer is not restarted for another full
interval in this time period, a system reset occurs when
the reset timeout expires. See Table 1.
The dedicated IR timer/counter module simplifies low-
speed infrared (IR) communication. The IR timer imple-
ments two pins (IRTX and IRRX) for supporting IR
transmit and receive, respectively. The IRTX pin has no
corresponding port pin designation, so the standard
PD, PO, and PI port control status bits are not present.
However, the IRTX pin output can be manipulated high
or low using the PWCN.IRTXOUT and PWCN.IRTXOE
bits when the IR timer is not enabled (i.e., IREN = 0).
15
to 2
24
system clock cycles. An interrupt is gener-
and Modulation Timer
IR Carrier Generation
WATCHDOG INTERRUPT (µs)
WATCHDOG RESET AFTER
Watchdog Timer
42.7
42.7
42.7
42.7
13