MAX5316 MAXIM [Maxim Integrated Products], MAX5316 Datasheet - Page 19

• Manufacturer Part Number: MAX5316
• Manufacturer: MAXIM [Maxim Integrated Products]

12, 19
PIN
10
11
13
14
15
16
17
18
19
20
21
22
23
24
—
5
6
7
8
9
AGND_S
AGND_F
BYPASS
AVDD1
AVDD2
READY
NAME
AGND
DGND
TC/SB
V
REFO
SCLK
AVSS
OUT
RFB
REF
RST
DIN
DDIO
CS
PD
EP
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SPI Bus Serial Data Input. See the Serial Interface section for details.
SPI Bus Serial Clock Input. See the Serial Interface section for details.
SPI Bus Active-Low Chip-Select Input. See the Serial Interface section for details.
DIN Format Select Input. Connect TC/SB to DGND to set the data input format to straight binary or to
VDDIO to set it to two’s complement.
Active-High Power-Down Input. Connect PD to DGND for normal operation. Connect PD to VDDIO to
place the device in power-down. In power-down, OUT (analog voltage output) is connected to AGND
through a 2kω resistor, but the contents of the input registers and the DAC latch do not change. The SPI
interface remains active in power-down.
Negative Analog Power-Supply Input. Connect to AGND or a negative supply voltage. When connected to
the negative supply voltage, bypass AVSS with a 0.1µF capacitor to AGND.
Analog Ground. Connect to the analog ground plane.
Positive Analog Power-Supply Input. Bypass each AVDD_ locally with a 0.1µF and 10µF capacitor to
AGND (analog ground plane). Connect AVDD1 and AVDD2 together.
Buffered Analog Voltage Output. Connect OUT to RFB externally to close the output buffer feedback loop.
The buffered output is capable of directly driving a 10kω load. The state of M/Z sets the power-on reset
state of OUT (zero or midscale). In power-down, OUT is connected to AGND through a 2kω pulldown
resistor.
Feedback Resistor Input. RFB is connected through the internal feedback resistor to the inverting input of
the analog output buffer. Externally connect RFB to OUT to close the output buffer feedback loop.
Voltage Reference Buffered Output. Bypass with a 100pF capacitor to AGND.
High-Impedance 10Mω Voltage Reference Input
DAC Analog Ground Sense
DAC Analog Ground Force. Connect to the analog ground plane.
Positive Analog Power-Supply Input. AVDD2 supplies power to the internal digital linear regulator. Bypass
AVDD2 locally to AGND with 0.1µF and 10µF capacitors. Connect AVDD2 and AVDD1 together.
Internal Bypass Connection. Connect BYPASS to DGND with 0.01µF and 1µF capacitors.
Digital Ground
Digital Interface Power-Supply Input. Connect to a 1.7V to 5.5V logic-level supply. Bypass V
0.1µF capacitor to DGND. The supply voltage at V
Active-Low Reset Input. Drive RST low to DGND to put the device into a reset state. A reset state sets all
SPI input registers to their default power-on reset states as defined by the state of inputs M/Z and TC/SB.
Set RST high to V
SPI Active-Low Ready Output. READY asserts low when the device successfully completes processing an
SPI data frame. READY asserts high at the next rising edge of CS. In daisy-chain applications, the READY
output typically drives the CS input of the next device in the chain or a GPIO of a microcontroller.
Exposed Pad. EP is internally connected to AGND. Connect to the analog ground plane.
16-Bit, ±1 LSB Accuracy Voltage Output
DDIO
, the DAC output remains at the state defined by M/Z until LDAC is taken low.
FUNCTION
DDIO
DAC with SPI Interface
sets the logic-level for the digital interface.
Pin Description (continued)
MAX5316
DDIO
with a