MAX533ACEE MAXIM [Maxim Integrated Products], MAX533ACEE Datasheet

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MAX533ACEE

Manufacturer Part Number
MAX533ACEE
Description
2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet

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MAX533ACEE
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MAX533ACEE
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The MAX533 serial-input, voltage-output, 8-bit quad
digital-to-analog converter (DAC) operates from a sin-
gle +2.7V to +3.6V supply. Internal precision buffers
swing rail to rail, and the reference input range includes
both ground and the positive rail. The MAX533 features
a 1µA shutdown mode.
The serial interface is double buffered: a 12-bit input
shift register is followed by four 8-bit buffer registers
and four 8-bit DAC registers. The 12-bit serial word
consists of eight data bits and four control bits (for DAC
selection and special programming commands). Both
the input and DAC registers can be updated indepen-
dently or simultaneously with a single software com-
mand. Two additional asynchronous control pins, LDAC
and CLR, provide simultaneous updating or clearing of
the input and DAC registers.
The interface is compatible with SPI™, QSPI™ (CPOL =
CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A
buffered data output allows daisy chaining of serial
devices.
In addition to 16-pin DIP and CERDIP packages, the
MAX533 is available in a 16-pin QSOP that occupies
the same area as an 8-pin SO.
________________________Applications
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
19-1080; Rev 0; 6/96
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
_______________General Description
__________________Pin Configuration
TOP VIEW
Digital Gain and Offset Adjustments
Programmable Attenuators
Programmable Current Sources
Portable Instruments
DOUT
OUTB
OUTA
LDAC
UPO
PDE
CLR
REF
________________________________________________________________ Maxim Integrated Products
1
2
3
4
5
6
7
8
DIP/QSOP
MAX533
2.7V, Low-Power, 8-Bit Quad DAC
16
15
14
13
12
11
10
9
OUTC
OUTD
AGND
V
DGND
DIN
SCLK
CS
with Rail-to-Rail Output Buffers
DD
____________________________Features
*Dice are tested at T
**Contact factory for availability and processing to MIL-STD-883.
Functional Diagram appears at end of data sheet.
______________Ordering Information
MAX533ACPE
MAX533BCPE
MAX533ACEE
MAX533BCEE
MAX533BC/D
MAX533AEPE
MAX533BEPE
MAX533AEEE
MAX533BEEE
MAX533AMJE
MAX533BMJE
+2.7V to +3.6V Single-Supply Operation
Ultra-Low Supply Current:
Ultra-Small 16-Pin QSOP Package
Ground to V
Output Buffer Amplifiers Swing Rail to Rail
10MHz Serial Interface, Compatible with SPI, QSPI
(CPOL = CPHA = 0 or CPOL = CPHA = 1), and
Microwire
Double-Buffered Registers for Synchronous
Updating
Serial Data Output for Daisy Chaining
Power-On Reset Clears Serial Interface and Sets
All Registers to Zero
Software Shutdown
Software-Programmable Logic Output
Asynchronous Hardware Clear Resets All Internal
Registers to Zero
0.7mA while Operating
1µA in Shutdown Mode
PART
DD
TEMP. RANGE
A
-55°C to +125°C 16 CERDIP**
-55°C to +125°C 16 CERDIP**
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
Reference Input Range
0°C to +70°C
= +25°C.
16 Plastic DIP
16 Plastic DIP
16 QSOP
16 QSOP
Dice*
16 Plastic DIP
16 Plastic DIP
16 QSOP
16 QSOP
PIN-PACKAGE
(LSB)
INL
±1
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2
1

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MAX533ACEE Summary of contents

Page 1

... Serial Data Output for Daisy Chaining Power-On Reset Clears Serial Interface and Sets All Registers to Zero Software Shutdown Software-Programmable Logic Output Asynchronous Hardware Clear Resets All Internal Registers to Zero ______________Ordering Information PART MAX533ACPE MAX533BCPE MAX533ACEE MAX533BCEE MAX533BC/D OUTC MAX533AEPE OUTD MAX533BEPE MAX533AEEE AGND MAX533BEEE V ...

Page 2

Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ABSOLUTE MAXIMUM RATINGS V to DGND ..............................................................-0.3V, + AGND...............................................................-0.3V, +6V DD Digital Input Voltage to DGND ....................................-0.3V, +6V Digital Output Voltage to DGND....................-0.3V, (V AGND to DGND ..................................................................±0.3V ...

Page 3

Low-Power, 8-Bit Quad DAC ELECTRICAL CHARACTERISTICS (continued +2.7V to +3.6V 2.5V, AGND = DGND = 0V REF Typical values are +3V and T = +25°C PARAMETER SYMBOL DIGITAL ...

Page 4

Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers TIMING CHARACTERISTICS (continued +2.7V to +3.6V 2.5V, AGND = DGND = 0V REF Typical values are +3V and T = +25°C.) DD ...

Page 5

Low-Power, 8-Bit Quad DAC __________________________________________Typical Operating Characteristics (V = +3V +25°C, unless otherwise noted DAC ZERO-CODE OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT 1.50 DAC CODE = 00 HEX 1.25 LOAD 1.00 0.75 ...

Page 6

Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ____________________________Typical Operating Characteristics (continued +3V +25°C, unless otherwise noted REFERENCE INPUT FREQUENCY RESPONSE -10 -15 - 0.1V SINE WAVE REF ...

Page 7

Low-Power, 8-Bit Quad DAC ____________________________Typical Operating Characteristics (continued +3V +25°C, unless otherwise noted POSITIVE SETTLING TIME MAX533-TOC15 5µs/div V = 3.0V DAC CODE = hex 2.5V NO ...

Page 8

Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers CS SCLK DIN MSB DACA DOUT MODE ...

Page 9

Low-Power, 8-Bit Quad DAC _______________Detailed Description Serial Interface At power-on, the serial interface and all digital-to- analog converters (DACs) are cleared and set to code zero. The serial data output (DOUT) is set to transition on SCLK's falling edge. ...

Page 10

Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers 12-BIT SERIAL WORD ...

Page 11

Low-Power, 8-Bit Quad DAC For this command, the data bits are “Don't Cares.” example, three MAX533s are daisy chained (A, B, and C), and devices A and C need to be updated. The 36-bit-wide command would consist ...

Page 12

Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers Interfacing to the Microprocessor The MAX533 is Microwire™ and SPI™/QSPI™ compati- ble. For SPI and QSPI, clear the CPOL and CPHA con- figuration bits (CPOL = CPHA = 0). The SPI/QSPI ...

Page 13

Low-Power, 8-Bit Quad DAC DIN SCLK LDAC CS1 CS2 CS3 CS MAX533 LDAC SCLK DIN Figure 7. Multiple MAX533s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an individual CS. Output Buffer Amplifiers ...

Page 14

Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers REF LSB DECODER DAC A Figure 8. DAC Simplified Circuit Diagram Power Sequencing The voltage applied to REF should not exceed V ...

Page 15

Low-Power, 8-Bit Quad DAC SYSTEM GND OUTC OUTD AGND Figure 10. Suggested PC Board Layout for Minimizing Crosstalk (Bottom View) _________________________________________________________Functional Diagram DOUT CLR LDAC UPO DECODE CONTROL 12-BIT SHIFT REGISTER SR CONTROL CS DIN SCLK ______________________________________________________________________________________ with Rail-to-Rail ...

Page 16

Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers ________________________________________________________Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit ...

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