STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet - Page 10

• Manufacturer Part Number: STLC5432Q
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STLC5432
XCLK (respectively Transmit Data and its clock
associated). Frame and multiframe generated by
the transmitter of the circuit are processed by the
receiver of the circuit, without encoding and de-
coding.
4.4 LOOPBACK 4
LP4 Command replaces Data in with Data out
near of DIN and DOUT pins (See LP4R register).
5 FRAME ALIGNMENT
Time slot 0 is used for the synchronization
(G.706). At software Reset Frame and Multiframe
are lost and a new research of FAS and MFAS is
launched.
5.1 LOSS OF FRAME ALIGNMENT
Frame alignment will be assumed to have been
lost :
Table 1: CRC4 Multiframe Structure G.704
10/46
FAS:
MFAS:
E1–E2:
C1 to C4:
A:
Sa4 to Sa8:
Sa61 to Sa64: ETSI bits
Multiframe
– either when three consecutive incorrect frame
alignment signals have been received,
Sub
II
I
Frame Alignment Signal in each even Time Slot.
Multi Frame Alignment Signal 0 0 1 0 1 1
CRC4 error Indication bits
Cyclic Redundancy Check 4 (CRC4) bits
Remote Alarm Indication
Five bits in each odd Time Slot
Frame
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
C1
C2
C3
C4
C1
C2
C3
C4
E1
E2
1
0
0
1
0
1
1
2
0
1
1
1
1
1
1
1
1
A
A
A
A
A
A
A
A
3
0
TIME SLOT ZERO BIT NUMBERS
5.2 FRAME ALIGNMENT RECOVERY
Frame alignment will be assumed recovered
when the following sequence is detected:
5.3 MULTIFRAME ALIGNMENT RECOVERY
Multiframe Alignment will be assumed recovered
when at least two valid multiframe alignment sig-
nals MFAS have been detected within 8 ms.
Sa4
Sa4
Sa4
Sa4
Sa4
Sa4
Sa4
Sa4
– or when bit 2 in time slot 0 in odd frames has
– or when 915 errored CRC blocks out of 1000
– Detection of the correct Frame Alignment Sig-
– detection of bit 2 of 32nd byte after FAS, at 1.
– detection of the correct Frame Alignment sig-
4
1
F
F
F
F
F
F
F
been received with an error, i.e. at 0, on three
consecutive occasions,
have been detected.
nal, FAS
nal in the 64th byte after the first FAS de-
tected.
Sa5
Sa5
Sa5
Sa5
Sa5
Sa5
Sa5
Sa5
A
A
A
A
A
A
A
5
1
Sa61
Sa62
Sa63
Sa64
Sa61
Sa62
Sa63
Sa64
S
S
S
S
S
S
S
6
0
Sa7
Sa7
Sa7
Sa7
Sa7
Sa7
Sa7
Sa7
7
1
Sa8
Sa8
Sa8
Sa8
Sa8
Sa8
Sa8
Sa8
8
1