STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet - Page 13

• Manufacturer Part Number: STLC5432Q
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

8.2 Serial Interface Mode
When an Alarm bit is put to 1 in ALR (Alarm Reg-
ister), this bit generates automatically the trans-
mission of two bytes message onto DOUT during
Time slot 0 with :
NB : When TSOR or Sa6R
(Complementary Alarm Register 1) is put to ”1”, it
generates a message in which there are address
and data of TSORR Register (if TSOR bit is not
masked), or address and data of Sa6RR register
(if Sa6R is not masked).
If the four occurences to transmit a message are si-
multaneous,the priority order is:
– The first bit of the first byte at 0; the second
– The data of the ALR (Alarm Register) is the sec-
bit is at 0 and after the address bits of Alarm
Register.
ondbyte.
bit of the CAR1
8.3 Stand Alone Mode
Interrupts are not generated.
AL0, AL1 pins indicate the current state of three
alarms : LOF, AIS, A bit received and DOUT pin
indicates the current state of nine alarms during
time-slot zero (See Par. 6.3).
Priority 1 :
Priority 2 :
Priority 3 :
Priority 4 :
Transmission of Alarm
Register data if an alarm
has been detected.
Transmission of Register
data after reading message
from remote entity.
Transmission of TSORR
data after loading of this
register.
Transmission of Sa6RR
data after loading of this
register.
STLC5432
13/46