STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet - Page 15

• Manufacturer Part Number: STLC5432Q
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

9.1 Reset Register
The software reset of the circuit is performed
when this register is addressed whatever the
value of its bits may be. Reading or writing is ir-
relevant. All the programmable registers are con-
figurated by the default value indicated in each
register description and the mechanism of multi-
frame is launched in accordance with the proce-
dure described in the introduction.
9.2 ALR: Alarm Register
LOS
AIS
915
LOF
SC
AR
EXT1 Extension bit 1.
9.3 AMR Alarm Mask Register
7
7
7
1
1
1
MEXT1 MAR MSC MLOF M915 MAIS MLOS
EXT1
Dummy Register
Loss of Signal.
This bit is set to 1 when ten consecutive
zeros have been detected before the
HDB3/BIN decoder.
Alarm Indication Signal:
this bit is set to 1 in accordance with G.775
when the incoming signal is recived with
only two, or less, zero for two consecutive
double frame period (i.e. 512 x 2 bit).
This bit is set to 1 when 915 errored CRC
message blocks have been received within
1 second.
Loss of Frame Alignment Word.
When at 1, the synchronization is lost.
One second Clock.
This bit is set to one every second when
there is synchronization. The number of
faults which have been counted during the
previous second is in fault counters FCR,
ECR and PCR.
A bit Received.
This bit is set to 1 when the bit 3 of the
odd time slot zero has been received
consecutively two times at 1.
This bit is set to 1 when one bit out of
CAR1 Register bits is put to 1.
AR
After Reset = FFH
After Reset = 88H
SC
LOF
915
AIS
LOS
0
0
0
This register can be written or read.
When a bit of this register is set to 1, the corre-
sponding bit of the ALR register, which has the
same number, is masked and an interrupt cannot
be generated by this bit.
9.4 CAR1: Complementary Alarm Register 1
7
WER
CRCF CRC Frame.
ER
TS0R Time slot Zero Register.
Sa6R Sa6R Register.
EXT2 EXTENSION Bit 2
9.5 CAMR1 Complementary Alarm Mask
This register can be read or written.
7
1 MEXT2 Nu MSaRm MTSOR MER MCRCF MWER
1
Register 1
EXT2
Frame Word Error Rate.
This bit is at ”1”when the threshold of fault
condition has been reached; this bit is at
”0” when the threshold of deactivating has
been reached. These two thresholds are
indicated by the error Rate Threshold
Register (ERTR). The Error Rate function
is validated when the synchronization is
achieved.
After remultiframe time, this bit is at ”1”
when an eight frame block has been
received with an error.
E Bit received.
ER bit is at ”1” during the frame 13
received when the E1 bit value of the same
frame 13 is zero.
ER bit is at ”1” during the frame 15 received
when the E2 bit value of the previous frame
15 is zero (E1 and E2 = first bit of time slot
zero in frames 13 and 15 respective).
Thisbit is at ”1” when the TS0RR Register has
been loaded in accordance withCR8
register and bit POLSa(CR6 register).
This bit is put to one when Sa6RR
Register has been loaded in accordance
with SaT bit (CR6 Register).
This bit is at ”1” when one bit out of
CAR2 Register bits has been set to ”1”.
0
After Reset = 80H
At Reset = FFH
Sa6R TS0R
ER CRCF WER
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